Fishing – trapping – and vermin destroying
Patent
1995-01-26
1997-03-25
Bowers, Jr., Charles L.
Fishing, trapping, and vermin destroying
437194, 437200, 437192, H01L 2144
Patent
active
056144377
ABSTRACT:
A method for manufacturing an ohmic contact on a semiconductor device, as disclosed herein, includes a first step of etching a via through a non-conductive layer formed over a partially fabricated version of the semiconductor device. This step exposes a region of a device element such as a source, gate electrode, etc. Next, an ohmic contact layer including tantalum and silicon is deposited over the partially fabricated device and in the vias by sputtering in an argon atmosphere. Thereafter, and in the same processing apparatus, a barrier layer including a tantalum silicon nitride is deposited over the ohmic contact layer. Then an aluminum alloy metallization layer is directly deposited on the partially fabricated device at a temperature of at least 650.degree. C. At this deposition temperature, the metallization layer conformally fills the via, thereby producing a stable, uniform contact.
REFERENCES:
patent: 4502209 (1985-03-01), Eizenberg et al.
patent: 4640004 (1987-02-01), Thomas et al.
patent: 4782380 (1988-11-01), Shankar et al.
patent: 4804636 (1989-02-01), Groover, III et al.
patent: 4888297 (1989-12-01), Aboelfotoh et al.
patent: 4912543 (1990-03-01), Neppl et al.
patent: 4981550 (1991-01-01), Huttemann et al.
patent: 5066615 (1991-11-01), Brady et al.
patent: 5135878 (1992-08-01), Bartur
patent: 5142438 (1992-08-01), Reinberg et al.
patent: 5231055 (1993-07-01), Smith
patent: 5240880 (1993-08-01), Hindman et al.
patent: 5275715 (1994-01-01), Tuttle
patent: 5278099 (1994-01-01), Maeda
patent: 5281838 (1994-01-01), Okumura
patent: 5312772 (1994-05-01), Yokoyama et al.
patent: 5341016 (1994-08-01), Prall et al.
patent: 5489548 (1996-02-01), Nishioka et al.
patent: 5504041 (1996-04-01), Summerfelt
Wolf et al., Silicon Processing for the VLSI Era, vol. I, Lattice Press, 1986, pp. 384-400.
Wolf et al., Silicon Processing for the VLSI Era, vol. II, Lattice Press, 1990, pp. 132-133.
Kolawa, Elzbieta; Halperin, Louis W., Vu, Quat; Nicolet, Marc-A; "Amorphous Ternary Thin-Film Alloys as Diffusion Barriers in Silicon Metallizations," pp. 243-247; California Institute of Technology; 1990.
Kwok, C.-K., Kolawa, E., Nicolet, M-A., Lee, Ray L.; "Stress and Resistivity in Reactively Supttered Amorphous Metallic Ta-Si-N Films"; California Institute of Technology.
Kolawa, E., Molarius, .sup.a) C.W. Nieh, M.-A. Nicolet, "Amorphous Ta-Si-N thin-film alloys as diffusion barrier in Al/Si metallizations;" pp. 3006-3010, J. Vac. Sci. Technol. A8 (3); American Vacuum Society; May/Jun. 1990.
Bowers Jr. Charles L.
Gurley Lynne A.
LSI Logic Corporation
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