Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-12-03
2003-08-19
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S466000, C438S486000
Reexamination Certificate
active
06607949
ABSTRACT:
This application claims the benefit of Korean Application No. P2000-85419 filed on Dec. 29, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a method for fabricating a polysilicon TFT. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving electrical characteristics of a polysilicon layer.
2. Discussion of the Related Art
In a conventional process for forming a polysilicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a plasma chemical vapor deposition (PCVD) method or a low pressure chemical vapor deposition (LPCVD) method. When the amorphous silicon layer has a thickness of about 500 Å (angstrom), it is recrystallized into a polysilicon layer by a crystallization method. The crystallization method is generally classified into a laser annealing method, a solid phase crystallization (SPC) method, and a metal induced crystallization (MIC) method.
In the laser annealing method, an insulating substrate having an amorphous silicon layer thereon is heated to a temperature of about 250° C. (degrees celsius). Thereafter, an eximer laser beam is applied to the amorphous silicon layer to form a polysilicon layer. For the SPC method, a heat-treatment is applied to the amorphous silicon layer at a high temperature for a long time to form the polysilicon layer. For the MIC method, a metal layer is deposited on the amorphous silicon layer and the deposited metal layer is used as a crystallization seed. In case of the MIC method, a large sized glass substrate may be used as the insulating substrate.
The laser annealing method is a recently widely researched method in forming a polysilicon layer. In the laser annealing method, laser energy is provided for an amorphous silicon layer formed on the insulating substrate, thereby melting the amorphous silicon layer. Then, the melted amorphous silicon is cooled to form polysilicon.
In case of the SPC method, a buffer layer is formed on a quartz substrate that can stand at a temperature higher than 600° C. (degrees celsius). The buffer layer serves to prevent spreading a contamination that results from the quartz substrate. Thereafter, the amorphous silicon is deposited on the buffer layer and is sufficiently heated in a furnace at a high temperature so as to form the polysilicon layer. However, because the SPC method is performed at the high temperature, it is difficult to acquire a desired polysilicon phase.
In the process of the SPC method, because polysilicon grains are developed without a continuous directionability, the polysilicon layer formed by the SPC method may have an irregular surface. For a thin film transistor, a gate insulating layer covers the polysilicon layer. Therefore, if the polysilicon layer has the irregular surface, the gate insulating layer is also formed with an irregular surface, thereby decreasing a breakdown voltage of the thin film transistor. Further, since size of the polysilicon grains is very irregular, electrical characteristics of a device adopting the polysilicon layer may be deteriorated in the SPC method. Furthermore, the quartz substrate used for the SPC method is very expensive. Thus, fabrication cost can be increased.
Unlike the SPC method that uses the expensive quartz substrate, the MIC method uses a relatively inexpensive glass substrate to form polysilicon. In case of applying the MIC method, however, metal impurities may remain in the polysilicon network, thereby deteriorating the quality of the polysilicon layer. Accordingly, other methods have been developed to improve the MIC method.
A field effect metal induced crystallization (FEMIC) method is an example of the improved MIC method. In the FEMIC method, after metal is deposited on a substrate, a high density direct current is applied to the metal to cause Joule heating. Because of the heated metal, an amorphous silicon formed on the heated substrate is crystallized into polysilicon. In this process, the metal serves as a catalyzer and is referred to as a catalytic metal.
FIGS. 1A
to
1
F illustrate a process of forming a polysilicon TFT according to the related art. The polysilicon TFT in this illustration is a coplanar type TFT having a top gate structure, and the FEMIC method is used to form the TFT.
In
FIG. 1A
, a first insulating layer
2
(i.e. a buffer layer) and an amorphous silicon layer
4
are sequentially deposited on a substrate
1
. The buffer layer
2
is to protect the amorphous silicon layer
4
from alkali substances, which may be produced from the substrate
1
during later processes. Generally the buffer layer
2
is formed of silicon oxide (SiO
2
). After the amorphous silicon layer
4
is formed, thin catalytic metal clusters
8
are formed thereon. Nickel (Ni) is typically selected for the catalytic metal among a transition metal such as nickel (Ni), paladium (Pd), iron (Fe), and cobalt (Co). The catalytic metal
8
is deposited using sputter, evaporater or metal solution. As a high density direct current
10
is applied to the catalytic metal
8
for generating heat, the catalytic metal
8
acts as a catalyzer in crystallization of the amorphous silicon layer
4
. In other words, silicide generated in the chemical reaction between the amorphous silicon layer
4
and the catalytic metal
8
acts as a seed of the crystallization.
In
FIG. 1B
, a power source
10
applies a high density direct current to the catalytic metal
8
, thereby crystallizing the amorphous silicon layer
4
(shown in
FIG. 1A
) into a polysilicon layer
5
. After the crystallization, the catalytic metal
8
is removed from the substrate
1
, and the polysilicon layer
5
is patterned into a polysilicon island
12
, as shown in FIG.
1
C.
In
FIG. 1D
, a second insulating layer
14
referred to as a gate insulating layer and a gate electrode
16
are sequentially formed on the polysilicon island
12
. Then, an ion doping is carried out injecting dopants into the polysilicon island
12
to form an active region
18
, a source region
20
, and a drain region
22
in the polysilicon island
12
. The active region
18
is a pure silicon region, whereas the source and drain regions
20
and
22
are doped silicon regions. The active region
18
is disposed on the buffer layer between the source and drain regions
20
and
22
, while the gate insulating layer
14
and the gate electrode
16
are positioned on the active region
18
.
Because the gate insulating layer
14
and the gate electrode
16
are patterned with the same mask in order to reduce the number of masks, they have the same shape. When the ion doping is applied to the polysilicon island
12
, the gate electrode
16
serves as an ion stopper to prevent the dopant from penetrating into the active region
18
. After the ion doping is finished, the polysilicon island
12
implements a specific electric characteristic, which varies with types of the dopants. If the dopant is, for example, B
2
H
6
that includes a Group III element, a doped portion of the polysilicon island
12
becomes a p-type semiconductor. Whereas, if the dopant is PH
3
that includes a Group VI element, the doped portion of the polysilicon island
12
becomes an n-type semiconductor. A proper dopant should be selected to satisfy the use of a device. After the dopant is applied onto the polysilicon island
12
, the dopant is activated.
In
FIG. 1E
, a third insulating layer
24
that serves as an interlayer insulating layer is formed to cover the gate electrode
16
, the active region
18
, and the source and drain regions
20
and
22
. A source contact hole
20
a
and a drain contact hole
22
b
are formed in the third insulating layer
24
, thereby exposing the source and the drain region
20
and
22
, respectively.
In
FIG. 1F
, a source electrode
26
and a drain electrode
28
are formed on the third insulating layer
24
. The source and the drain electrode
26
and
2
Kim Binn
Kim Hae Yeol
Nam Dae Hyun
LG.Philips LCD Co. , Ltd.
Morgan & Lewis & Bockius, LLP
Niebling John F.
Roman Angel
LandOfFree
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