Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-07-27
2002-03-26
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S101000, C257S620000
Reexamination Certificate
active
06362651
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to programmable logic devices (PLDs), and more particularly to a layout architecture and method for fabricating PLDs including multiple discrete devices formed on a single semiconductor substrate (chip).
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) typically include a plurality of logic elements and associated interconnect resources that are programmed by a user to implement user-defined logic operations (e.g., an application specific circuit design). A PLD is typically programmed using programming software that is provided by the PLD's manufacturer, a personal computer or workstation capable of running the programming software, and a device programmer. In contrast, application specific integrated circuits (ASICs) have fixed-function logic circuits and fixed signal routing paths, and require a protracted layout process and an expensive fabrication process to implement a user's logic operation. Because PLDs can be utilized to implement logic operations in a relatively quick and inexpensive manner, PLDS are often preferred over ASICs for many applications.
FIG.
1
(A) shows an example of a field programmable gate array (FPGA)
100
, which is one type of PLD. Although greatly simplified, FPGA
100
is generally consistent with XC
3000
™ series FPGAs, which are produced by Xilinx, Inc. of San Jose, Calif.
FPGA
100
includes an array of configurable logic blocks (CLBs)
1
,
1
through
4
,
4
surrounded by input/output blocks (IOBs) IOB-
1
through IOB-
16
, and programmable interconnect resources that include vertical interconnect segments
120
and horizontal interconnect segments
121
extending between the rows and columns of CLBs and IOBs. The CLBs, IOBs and programmable interconnect resources of FPGA
100
form a discrete circuit that resides on a silicon chip.
Each CLB includes configurable combinational circuitry and optional output registers that are programmed to implement logic in accordance with CLB configuration data stored in configuration memory cells (not shown) of FPGA
100
. Data is transmitted into each CLB on input wires
110
and is transmitted from each CLB on output wires
115
. The configurable combinational circuitry of each CLB implement a portion of a logic operation responsive to signals received on input wires
110
in accordance with the CLB configuration data stored in the configuration memory cells associated with that CLB. Similarly, the optional output registers of each CLB transmit signals from the CLB onto a selected output wire
115
in accordance with the stored CLB configuration data. Typically, all of the CLBs of an FPGA include identical configurable circuitry.
Each IOB includes configurable circuitry that is controlled by associated configuration memory cells, which are programmed to store IOB configuration data. In accordance with the IOB configuration data, each IOB selectively allows an associated pin (not shown) of FPGA
100
to be used either for receiving input signals from other devices, or for transmitting output signals to other devices. Similar to the CLBs, all of the IOBs of an FPGA typically include identical configurable circuitry.
The programmable interconnect resources of FPGA
100
are configured using various switches to generate signal paths for passing input and output signals between the CLBs and IOBs. These various switches include segment-to-segment switches, segment-to-CLB/IOB input switches, and CLB/IOB-to-segment output switches. Segment-to-segment switches include configurable circuitry that selectively connects wiring segments to form signal paths. Segment-to-CLB/IOB input switches include configurable circuitry that selectively connects the input wire
110
of a CLB (or IOB) to the end of a signal path. CLB/IOB-to-segment output switches include configurable circuitry that selectively connects the output wire
115
of a CLB (or IOB) to the beginning of a signal path.
FIG.
1
(B) shows an example of a six-way segment-to-segment switch
122
that selectively connects vertical wiring segments
120
(
1
) and
120
(
2
), and horizontal wiring segments
121
(
1
) and
121
(
2
), in accordance with 6-way switch configuration data stored in configuration memory cells M
1
through M
6
. Six-way switch
122
includes normally-open pass transistors that are turned on to provide a signal path (or branch) between any two (or more) of the wiring segments in accordance with the 6-way switch configuration data. For example, a signal path is provided between vertical wiring segment
120
(
1
) and vertical wiring segment
120
(
2
) by programming memory cell M
5
to turn on its associated pass transistor. Similarly, a signal path is provided between vertical wiring segment
120
(
1
) and horizontal wiring segment
121
(
2
) by programming memory cell M
1
to turn on its associated pass transistor. Similar signal paths between any two (or more) wiring segments are provided by selectively the relevant memory cell (or memory cells).
FIG.
1
(C) shows an example of a segment-to-CLB/IOB input switch
123
that selectively connects an input wire
110
(
1
) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with input switch configuration data stored in configuration memory cells M
7
and M
8
. Segment-to-CLB/IOB input switch
123
includes a multiplexer (MUX) having inputs connected to horizontal wiring segments
121
(
3
) through
121
(
5
) through buffers, and an output that is connected to CLB/IOB input wire
110
(
1
). Memory devices M
7
and M
8
transmit control signals on select lines of the MUX such that the MUX passes a signal from one of the wiring segments
121
(
3
) through
121
(
5
) to the associated CLB (or IOB).
FIG.
1
(D) shows an example of a CLB/IOB-to-segment output switch
124
that selectively connects an output wire
115
(
1
) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with input switch configuration data stored in configuration memory cells M
9
through M
11
. CLB/IOB-to-segment output switch
124
includes three pass transistors connected between output wire
115
(
1
) and horizontal wiring segments
120
(
3
) through
120
(
5
), and gates that are connected memory cells M
9
through M
11
. Memory devices M
9
through M
11
store output switch configuration data that turns on selected pass transistors to pass output signals from the CLB (or IOB) to one or more of wiring segments
120
(
3
) through
120
(
5
).
As with most types of integrated circuits, PLD circuits are fabricated on silicon wafers using known silicon processing techniques. After the PLD circuits are formed, the wafers are diced into individual “chips”, each chip including one PLD circuit. These chips are then packaged using known packaging technologies to form PLDS.
FIG.
2
(A) is a simplified plan view showing a silicon wafer
200
that is fabricated to include multiple discrete circuits
210
, each circuit
210
corresponding to one conventional FPGA
100
(see FIG.
1
(A)). Each circuit
210
is separated from other circuits on wafer
200
by horizontal scribe lines
220
and vertical scribe lines
230
. These scribe lines provide a predetermined distance between adjacent circuits
210
to prevent damage during the dicing process.
FIG.
2
(B) is an enlarged view showing additional details regarding the fabrication of circuits
210
on wafer
200
. In particular, FIG.
2
(B) shows a portion of a row including circuits
210
(
1
) and
210
(
2
), each depicted with circuitry corresponding to the CLBs, IOBs and interconnect lines of FPGA
100
(see FIG.
1
(A)). Circuit
210
(
1
) is formed in an area defined by horizontal scribe lines
220
(
1
) and
220
(
2
), and vertical scribe lines
230
(
1
) and
230
(
2
). Similarly, circuit
210
(
2
) is formed in an area defined by horizontal scribe lines
220
(
1
) and
220
(
2
), and vertical scribe lines
230
(
2
) and
230
(
3
). Note that circuit
210
(
1
) is completely separated (electrically isolated) by vertical scribe line
230
(
2
) from circuit
210
(
2
Beyer Hoffman & Harms LLP
Tokar Michael
Tran Anh
Xilinx , Inc.
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