Method for fabricating of super self-aligned bipolar transistor

Details Method for fabricating of super self-aligned bipolar transistor Method for fabricating of super self-aligned bipolar transistor

1999-01-13

2001-02-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S031000, C438S309000

Reexamination Certificate

active

06190984

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a super self-aligned bipolar transistor and method for fabricating thereof and, more particularly, to a super self-aligned heterojunction bipolar transistor and method for manufacturing thereof through the use of a selective collector epitaxial growth process.
BACKGROUND OF THE INVENTION
In general, even if the prior art element has an improved operating speed in proportion to miniaturization of a homojunction bipolar transistor, since, to accomplish this, an impurity concentration between emitter and base should be increased, enhancement of characteristics thereof based on a structure of such element is a difficult task.
There have been proposed a heterojunction bipolar transistor to cope with the above disadvantage.
Such heterojunction bipolar transistor has a characteristics that energy bandgap of an emitter is larger than that of a base. For this reason, utilizations of the heterojunction bipolar transistor showed an improvement of the performance of element and various design effects in comparison to the homojunction bipolar transistor. In addition, in the manufacturing process associated with the homojunction bipolar transistor previously described, there have been developed a method of decreasing the energy bandgap by adding germanium to a base layer composed of silicon.
As a conventional homojunction silicon bipolar transistor, the prior art heterojunction bipolar transistors utilizes a polysilicon thin film as both a base electrode and a impurity diffusion source for an emitter.
Thus, using Ge instead of Si on the base layer, a difference between an energy bandgap of the emitter and that of the base is occurred to increase an emitter implantation efficiency, then the base is grown to a high doping concentration ultra-thin film, thereby enhancing a current gain and a switching speed of element.
Recently, according as the optimization and the miniaturization of the structure of element, there have being utilized various methods to minimize several parasitic components such as a base resistance causing at an active region of the element and a parasitic capacity causing between a collector and a base.
Examples of such various methods is a trench isolation, a local oxidation of silicon (“LOCOS”), a selective epitaxial growth (“SEG”) of a SiGe base thin film, and a selective epitaxial growth for a Si emitter and so on.
Using the above methods, there have being developed a super self-aligned Si/SiGe heterojunction bipolar transistor which self-aligned between base and emitter to reduce a base parasitic resistance, or self-aligned both between base and emitter, and between collector and base.
Furthermore, in order to further reduce the base parasitic resistance resulting from the poly-silicon thin film forming a base electrode material, developments of manufacture process using as the base electrode a metallic thin film for example titanium silicide, instead of the polysilicon thin film have being performed.
The above local oxidation of silicon method has a shortcoming that a bird's beak is horizontally formed as a thickness of silicon thermal oxidation film, resulting in a limitation of geometric reduction of the element.
There are shown in
FIG. 1
an exemplary super self-aligned Si/SiGe heterojunction bipolar transistor which utilizes the selective epitaxial growth method for a SiGe base thin film without using the LOCOS method.
Referring to
FIG. 1
, there are shown a cross-sectional view of npn Si/SiGe heterojunction bipolar transistor which self-aligned between collector and base by using the selective base epitaxial growth previously described, after the growth of a base thin film.
An n
+
buried silicon collector layer (
1
-
2
) is first formed on a p-type silicon substrate (
1
-
1
), and an n-silicon collector layer (
1
-
3
) is then grown on the buried collector layer (
1
-
2
).
Subsequently, a collector junction portion (
1
-
4
) is formed by implanting an n-type impurity ion thereon, and then a trench to isolate between elements is formed by a dry etching method, and, in turn, filling therein with Boron Phosphorous Silica Glass (“BPSG”) insulating thin film (
1
-
5
) made of boron B and phosphorous P. The BPSG insulating thin film (
1
-
5
) is then flatted under a high pressures.
In an ensuing step, an insulating film (
1
-
6
), a P
+
polysilicon film (
1
-
7
), an insulating film (
1
-
8
) and a side-wall insulating film (
1
-
9
) are formed by depositing and etching methods as shown in
FIG. 1
, and an n-type collector region (
1
-
10
) for enhancing characteristics of elements in a high current region is then formed by selectively ion implanting to only an active region of the element.
In a subsequent step, a SiGe base layer (
1
-
11
) is selectively grown on only an exposed portion in the collector region (
1
-
10
) and the polysilicon film (
1
-
7
), through the use of Gas Source Molecular Beam technique, and then a polysilicon film (
1
-
12
) is selectively grown on the remaining space, thereby accomplishing junction between the polysilicon film (
1
-
7
) for a base electrode and the SiGe base layer (
1
-
11
).
Accordingly, self-alignment between the collector and the base can be performed, since a parasitic capacity region formed between the collector and the base is not defined as a photoresist and is limited only portion of a polysilicon thin film (
1
-
12
).
Since, however, the parasitic capacity region defined by the polysilicon thin film (
1
-
12
) is determined from a horizontal wet etching for the insulating film (
1
-
6
), resulting in the degradation of efficiency of process in an uniformity and a reproduction aspects, thus entailing the fatal degradation of the performance of element.
In addition, the prior art method has a disadvantage that since the low speed selective epitaxial growth method is applied two times during the growth of the SiGe base layer (
1
-
11
) and the poly-silicon thin film (
1
-
12
), and two thin film for example, the SiGe base (
1
-
11
) and the polysilicon (
1
-
12
), are used during the growth process thereof, resulting in a complicated manufacture process, and further even if the polysilicon thin film (
1
-
12
) is slightly grown on the base layer (
1
-
11
), it is allow to cause the fatal degradation of element performance, thereby making it difficult to control the process thereof. Thus, the prior art method is difficult to accomplish an effective manufacturing process and a simplified process step.
Furthermore, as shown in
FIG. 1
, the prior art method has a shortcoming that a trench structure for isolating between elements should be deeply formed so as to prevent the collector junction portion (
1
-
4
) from contacting between elements via the n
−
collector thin film (
1
-
3
) on the n
+
buried Si collector layer (
1
-
2
) formed at the entire surface of a substrate, resulting in a larger space requirement to fill with the insulating thin film (
1
-
5
), thus entailing a bulkier element.
Tuning now to
FIG. 2
, there are presented a cross-sectional view of Si/SiGe heterojunction bipolar element manufactured by another method previously described, after the growth of a base thin film.
In the prior art exemplary shown in
FIG. 2
, both of the base and the collector thin films are grown through the use of selective epitaxial growth method in contrast with the trench structure previously described, to thereby accomplish a simplified and an integrated manufacture processes.
As shown in
FIG. 2
, an n
+
-type collector (
2
-
2
) is first formed on a p-type substrate (
2
-
1
), and then an insulating thin film (
2
-
3
) and a polysilicon thin film (
2
-
4
) for a base electrode are sequently deposited thereon, thereafter, a base electrode region is defined by a photoresist mask and etching the poly-silicon thin film (
2
-
4
).
After the above step, a insulating thin film (
2
-
5
) is deposited thereon, and then the photoresist mask, the insulating thin film (
2
-
5
), the poly-silicon thin film (
2
-
4
) and the insulating thin fil

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