Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Dopant introduction into semiconductor region
Reexamination Certificate
2005-07-26
2005-07-26
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Dopant introduction into semiconductor region
C438S047000, C438S495000, C257SE21110
Reexamination Certificate
active
06921678
ABSTRACT:
The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.
REFERENCES:
patent: 5543354 (1996-08-01), Richard et al.
patent: 5856209 (1999-01-01), Imanishi
patent: 5888886 (1999-03-01), Sverdlov et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6060335 (2000-05-01), Rennie et al.
patent: 6172382 (2001-01-01), Nagahama et al.
patent: 08-97471 (1996-04-01), None
Van Zant, Peter; Microchip Fabrication (2000); McGraw-Hill, Fourth Edition; pp. 348-349.
K. Kumakura et al., “Increased Electrical Activity of Mg-Acceptors in A1xGa1-xN/GaN Superlattices”: Japanese Journal of Applied Physics, vol. 38 (1999), pp. L1012-L1014, Part 2, No. 9A/B, Sep. 15, 1999.
T. Nishida et al., “Selectively Enhanced Mg Incorporation into A1GaN Barrier Layer of Strained-Layer-Superlattice”:Proc. 61th Appl. Phys. Conf.,Hokkaido, Japan, Sep., 2000, p. 286, 3a-Y-30 and an English translation thereof.
Ban Yuzaburo
Harafuji Kenji
Hasegawa Yoshiaki
Ishibashi Akihiko
Miyanaga Ryoko
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Smoot Stephen W.
Studebaker Donald R.
LandOfFree
Method for fabricating nitride semiconductor, method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating nitride semiconductor, method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating nitride semiconductor, method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3426592