Method for fabricating multi-level interconnection

Details Method for fabricating multi-level interconnection Method for fabricating multi-level interconnection

1996-06-19

1999-02-09

Wojciechowicz, Edward

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438639, H01L 214763

Patent

active

058693939

ABSTRACT:
The present invention discloses a method of fabricating a multi-level interconnection on semiconductor substrate. A dielectric layer is formed on the substrate, and a first conductive layer is formed on the dielectric layer. An IMD layer is formed on the first conductive layer, a buffer layer is formed on the first IMD layer, a second conductive layer is formed on the buffer layer, and a second metal dielectric layer having a hole with a shallow trench is formed on the buffer layer. The width of the second conductive layer is the same with the width of the hole. A third conductive layer is formed, filling the shallow trench. The third conductive layer also contacts a sidewall of the hole and is accessible from the top of the second metal dielectric layer.

REFERENCES:
patent: 4656732 (1987-04-01), Teng et al.
patent: 5106780 (1992-04-01), Higuchi
patent: 5244837 (1993-09-01), Dennison
patent: 5330934 (1994-07-01), Shibata et al.
patent: 5543360 (1996-08-01), Matsuoka et al.

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