Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2000-01-04
2003-03-18
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S458000
Reexamination Certificate
active
06534381
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique including a method and device for bonding a first substrate to a second substrate for the manufacture of semiconductor integrated circuits, for example. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, photonic devices, piezoelectronic devices, microelectromechanical systems (“MEMS”), sensors, actuators, solar cells, flat panel displays (e.g., LCD, AMLCD), biological and biomedical devices, and the like.
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs.
Some integrated circuits are fabricated on a slice or wafer, of single-crystal (i.e., monocrystalline) silicon, commonly termed a “bulk” silicon wafer. Devices on such a “bulk” silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon (“LOCOS”) process, trench isolation, and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip. Additionally, trench isolation often requires a process of reactive ion etching, which is extremely time consuming and can be difficult to achieve accurately. Bulk silicon wafers, which are greater than 200 millimeters, are not free from defects and can reduce overall devices yields and the like.
An approach to achieving very-large scale integration (“VLSI”) or ultra-large scale integration (“ULSI”) uses epitaxial silicon wafers, which are commonly known as “epi-wafers.” Epi-wafers often have a layer of high quality single crystalline silicon material defined overlying a face of a bulk substrate. The high quality silicon layer provides a good site for fabricating devices, often with higher yields, than conventional bulk silicon wafer materials. The high quality silicon material is often deposited by way of epitaxial silicon process reactors made by companies called Applied Materials, Inc. of Santa Clara, Calif. or ASM of Phoenix, Ariz.
Epitaxial wafers offer other advantages over bulk silicon technologies as well. For example, epitaxial wafers have almost perfect crystalline characteristics, which enhance device speed, functionality, and reliability. Additionally, the epitaxial wafers often provide higher device yields, than conventional bulk wafers. Many problems, however, than have already been solved regarding fabricating devices on bulk silicon wafers remain to be solved for fabricating devices on epitaxial silicon wafers. Epitaxial silicon wafers are made by way of epitaxial reactors, which are often expensive to purchase and difficult to maintain. The process of forming epitaxial silicon is also slow and time consuming. Accordingly, resulting epitaxial silicon wafers can often be expensive and cannot be used for the manufacture of many commercial or commodity devices such as dynamic random access memory devices (i.e., DRAMs), for example.
From the above, it is seen that an improved technique for manufacturing a multi-layered wafer is highly desirable.
SUMMARY OF THE INVENTION
According to the present invention, a technique including a method and device for fabricating substrates is provided. In a specific embodiment, the present invention provides a method for bonding a first substrate to a second substrate with a compliant layer sandwiched in between. In an exemplary embodiment using silicon substrates, the present technique can occur at a low temperature, which ranges from about 200 degrees Celsius and less.
In a specific embodiment, the present invention provides a method for fabricating a substrate such as an epi-like substrate and others. Here, the term epi-like substrate generally means a multi-layered substrate such as a silicon-on-silicon structure that has a high quality single crystal silicon material overlying bulk silicon made by a layer transfer process, rather than conventional epitaxial silicon deposition processes. The method includes providing a first substrate having a substantially planar surface. The first substrate can be of a first substrate type, e.g., silicon, polysilicon, and compound semiconductor. The method includes implanting a plurality of particles into and through the substantially planar surface to a selected depth to define a volume of implanted material within the substrate. The implanted material has an amorphous characteristic from the selected depth to the substantially planar surface. To bond substrates together, the method contacts a face of a second substrate against the substantially planar implanted surface. The amorphous characteristic of the substantially planar surface provides a compliant layer for embedding one or more surface non-uniformities (e.g., particles, hillocks) into the compliant layer to bring a greater portion of the substrate surfaces together.
In an alternative embodiment, the present invention provides a partially completed semiconductor substrate, which is desirable for bonding purposes. The substrate has a substantially planar surface. A volume of substrate material comprising particles implanted through the substantially planar surface to a selected depth also is included. The volume of substrate material has a compliant characteristic from an amorphous material from the selected depth to the substantially planar surface. The implanted substantially planar surface is activated to be bonded to a second surface. Additionally, the compliant characteristic allows a surface imperfection on one or more surfaces to be embedded into the volume of the substrate material, which tends to bring more of the substantially planar surface to be contacted to the second surface.
Numerous benefits are achieved using the present invention over the pre-existing techniques. For example, the present invention provides an efficient technique for forming multi-layered substrates using a lower temperature bonding process. The lower temperature bonding process allows the present invention to be used for the manufacture of substrates using a layer transfer process such as the Controlled Cleavage Process of Silicon Genesis Corporation or Smart Cut™ of a company called Soitec. In some embodiments, the present invention can be implemented using conventional tools such as ion implantation equipment and the like. Additionally, the present invention can be used to form a high quality “epi-like” wafer, which has a high quality layer of silicon material overlying a bulk substrate, to form a silicon-on-silicon multi-layered substrate structure. The epi-like wafer is made by way of a layer transfer process. The epi-like wafer also electrically contacts the high quality silicon layer to the bulk silicon substrate in an epi-like manner. Depending upon the embodiment, one or more of these benefits may be achieved. A further discussion of these and other benefits are described throughout the present specification and more particularly below.
These and other embodiments of the present invention are described in more detail in conjunction with the text below and attached Figs.
REFERENCES:
patent: 4638552 (1987-01-01), Shimbo et al.
patent: 4968628 (1990-11-01), Delgado et al.
patent: 5236118 (1993-08-01), Bower et al.
patent: 545
Cheung Nathan W.
En William G.
Farrens Sharon N.
Korolik Mikhail
Blum David S
Chaudhuri Olik
Silicon Genesis Corporation
Townsend and Townsend / and Crew LLP
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