Fishing – trapping – and vermin destroying
Patent
1995-05-22
1997-01-07
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437240, 437950, H01L 21225
Patent
active
055916678
ABSTRACT:
A method for fabricating an MOS transistor includes the steps of forming a gate insulating layer on a substrate of a first conductivity-type, forming a gate on the gate insulating layer, forming a disposable layer over an entire surface of the substrate and the gate, the disposable layer having a first conductivity-type impurity and a second conductivity-type impurity of a higher concentration than that of the first conductivity-type impurity, and forming a source and drain area of the second conductivity-type impurity on the substrate by diffusing the second conductivity-type impurity of the disposable layer into the substrate by means of an annealing process, wherein the disposable layer includes a BPSG layer.
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Paper Entitled "An SPDD P-Mosfet Structure Suitable for 0.1 and Sub 0.1 Micron Channel Length and its Electrical Characteristics," by M. Saito, et al., Presented at the International Electron Devices Meeting, Dec. 13-16, 1992.
Wolf, "Silicon Processing for the VLSI Era", 1986 pp. 189-191.
Byun Jeong S.
Choi Sang J.
Chaudhari Chandra
LG Semicon Co. Ltd.
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