Method for fabricating MOS-FET

Details Method for fabricating MOS-FET Method for fabricating MOS-FET

2007-09-11

2010-10-12

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C257S348000, C257S349000, C257SE21409

Reexamination Certificate

active

07811873

ABSTRACT:
A method for fabricating MOS-FET using a SOI substrate includes a process of ion implantation of an impurity into a channel region in a SOI layer; and a process of channel-annealing in a non-oxidized atmosphere. In the ion implantation process, a concentration peak of the impurity is made to exist in the SOI layer. Moreover in the channel-annealing process, the impurity is distributed with a high concentration in the vicinity of the surface of the SOI layer under the following condition with the anneal temperature as T (K) and annealing time as t (minutes):in-line-formulae description="In-line Formulae" end="lead"?506×1000/T−490<t<400×1000/T−386.in-line-formulae description="In-line Formulae" end="tail"?

REFERENCES:
patent: 6825074 (2004-11-01), Miura
patent: 6861322 (2005-03-01), Hirashita et al.
patent: 2003/0122164 (2003-07-01), Komatsu
patent: 2009/0023269 (2009-01-01), Morimoto et al.
patent: 2000-349295 (2000-12-01), None
patent: 2002270846 (2002-09-01), None

Affiliated with

Also associated with

Rating

Method for fabricating MOS-FET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating MOS-FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating MOS-FET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4184349