Method for fabricating microbump interconnect for bare semicondu

Details Method for fabricating microbump interconnect for bare semicondu Method for fabricating microbump interconnect for bare semicondu

1996-03-18

1998-08-04

Niebling, John

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

H01L 2100

Patent

active

057892717

ABSTRACT:
A method for forming an interconnect for making a temporary or permanent electrical connection to a semiconductor dice is provided. The interconnect includes a rigid substrate on which an insulating layer and a pattern of conductors are formed. A compliant layer is formed on the insulating layer of a material such as polyimide. Vias are formed in the compliant layer with metal contacts in electrical communication with the conductors. Microbumps are formed on the compliant layer in electrical communication with the contacts and are adapted to flex with the compliant layer. The interconnect can be used to provide a temporary electrical connection for testing bare semiconductor dice. Alternately the interconnect can be used for flip chip mounting dice for fabricating multi chip modules and other electronic devices.

REFERENCES:
patent: 3461357 (1969-08-01), Mutter et al.
patent: 4005472 (1977-01-01), Harris et al.
patent: 4661375 (1987-04-01), Thomas
patent: 4764804 (1988-08-01), Sahara et al.
patent: 5072289 (1991-12-01), Sugimoto et al.
patent: 5090118 (1992-02-01), Kwon et al.
patent: 5123850 (1992-06-01), Elder et al.
patent: 5225037 (1993-07-01), Elder et al.
patent: 5262718 (1993-11-01), Svendsen et al.
patent: 5289631 (1994-03-01), Koopman et al.
patent: 5302891 (1994-04-01), Wood et al.
patent: 5329423 (1994-07-01), Scholz
patent: 5367253 (1994-11-01), Wood et al.
patent: 5408190 (1995-04-01), Wood et al.
patent: 5426072 (1995-06-01), Finnila
patent: 5438223 (1995-08-01), Higashi et al.
patent: 5440240 (1995-08-01), Wood et al.
patent: 5487999 (1996-01-01), Farnworth
patent: 5492235 (1996-02-01), Crafts et al.
patent: 5534465 (1996-07-01), Frye et al.
patent: 5602422 (1997-02-01), Schuellet et al.
patent: 5661336 (1997-08-01), Phelps, Jr. et al.
patent: 5678301 (1997-10-01), Gochnour et al.
Kuhn et al, "High density, Low-Temperature Solder Reflow Bonding of Silicon Chips to Plastic Substrates", IBM Tech. Disc. Bull., vol. 18, No. 10, p. 3477, Mar. 1976.
"Solder Bump Formation on Via Holes", IBM Tech. Disc. Bull., vol. 37, No. 06B, p. 299, Jun. 1994.
Yamamoto, Yashuhikio et al., "Evaluation of New Micro-Connection System Using Microbumps", Nitto Denko Corp., Technical Paper, ISHM '93 Proceedings, pp. 370-378, 1993.
Miyake, Koyoshi et al., "Connectivity Analysis of New `Known Good Die` Connection System Using Microbumps", Technical Report, Nitto Denko Corp., pp. 1-7, 1994.
"Science Over Art. Our New IC Membrane Test Probe." Packard Hughes Interconnect Advertising Brochure, 1993.

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