Method for fabricating metal line in a semiconductor

Details Method for fabricating metal line in a semiconductor Method for fabricating metal line in a semiconductor

2007-11-27

2007-11-27

Luu, Chuong A. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S622000, C438S687000

Reexamination Certificate

active

11177920

ABSTRACT:
A metal line is fabricated in a semiconductor device by a method including: forming an etch stop layer on a substrate; forming an interlayer insulating layer on the etch stop layer, the interlayer insulating layer including dual damascene patterns, each respectively having a trench and a via contact hole; forming a barrier metal layer and a line metal layer on the interlayer insulating layer and in the dual damascene patterns; forming an anti-oxidation layer on above the line metal layer; and forming a metal line in the dual damascene patterns by planarizing an entire surface of the anti-oxidation layer.

REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 6566242 (2003-05-01), Adams et al.
patent: 6589863 (2003-07-01), Usami
patent: 7144811 (2006-12-01), Liu et al.
patent: 2005/0001318 (2005-01-01), Won
patent: 2005/0245072 (2005-11-01), Lee et al.

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