Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-01
2004-01-13
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S424000, C438S622000
Reexamination Certificate
active
06677232
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the fabrication of semiconductor devices and, more particularly, to a method for fabricating metal conductors and multi-level interconnects in a semiconductor device.
BACKGROUND OF THE INVENTION
Trenches or channels and other types of regions are often formed in a dielectric substrate of a semiconductor device to form conductors made of copper, copper alloys or other conducting materials. For example, trench patterns may be etched, or formed using other suitable methods, and subsequently filled with a conducting material. Additionally, because the conducting material may diffuse rapidly into other materials, such as the dielectric material, a diffusion barrier may also be deposited onto the dielectric material and the surfaces of the trench. Similarly, vias may be formed and filled with a conducting material, such as copper, copper alloys, or other suitable conducting materials, to provide a multi-level interconnect between two or more trench patterns.
However, as the width of the trench or via decreases, or as the depth of the trench or via increases, filling the trench or via with the conducting material becomes increasingly difficult. For example, as the conducting material is deposited into the trench or via, an overhang of the conducting material at or near upper portions of the opposing sidewalls of the trench or via may result in premature contact of the conducting material from the opposing sidewalls, thereby resulting in a void or cavity formation within the conducting material. Further, as the aspect ratio, or the depth-to-width ratio, of the trench or via increases, voids or other discontinuities within the conducting material may occur during filling of the trench or via.
Additionally, if the temperature of the conducting material is increased to obtain improved mobility of the conducting material during filling of the trench or via, agglomeration of the conducting material may result along the sidewalls and bottom surface of the trench or via, thereby resulting in discontinuities on the conducting material. Agglomeration of the conducting material may also result during filling of the trench or via as the thickness of a layer of the conducting material decreases.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a method for fabricating a metal conductor or multi-level interconnect in a semiconductor device which reduces the likelihood of voids or other discontinuities within the conducting materials. The present invention provides a method for fabricating metal conductors and multi-level interconnects in a semiconductor device that addresses shortcomings of prior semiconductor fabrication methods.
According to one embodiment of the present invention, a method for fabricating a metal conductor in a semiconductor device includes forming a trench in a dielectric layer of the semiconductor device and depositing a first conducting material within the trench to form a continuous liner layer within the trench. The liner layer is formed at a first temperature. The method also includes filling a remaining portion of the trench over the liner layer with a second conducting material at a second temperature. The second temperature is greater than the first temperature.
According to another embodiment of the present invention, a method for fabricating a multi-level interconnect in a semiconductor device includes forming a first trench in a first dielectric layer of the semiconductor device and forming a via extending from the first trench to a second trench disposed in a second dielectric layer of the semiconductor device. The second trench comprises a metal conductor, and a dielectric barrier is disposed between the first and second dielectric layers. The method also includes depositing a first conducting material within the first trench and the via to form a continuous liner layer within the first trench and the via. The liner layer is formed at a first temperature. The method further includes filling a remaining portion of the first trench and the via over the liner layer with a second conducting material to form the multi-level interconnect between the first trench and the second trench. The remaining portion of the first trench and the via are filled at a second temperature which is greater than the first temperature.
An important technical advantage of the present invention is that the continuous liner layer within the trench increases the mobility of the conducting material as the conducting material is deposited within the trench, thereby substantially eliminating premature contact of the conducting material from opposing sidewalls of the trench during filling of the trench and substantially preventing the formation of voids or other discontinuities within the conducting material.
Additionally, in one embodiment, the liner layer may be formed via chemical vapor deposition at a generally low temperature, for example, between 20-200 degrees Celsius, thereby substantially reducing the likelihood of agglomeration of the conducting material within the trench. A remaining portion of the trench may then be filled with the conducting material using a variety of techniques with the liner layer providing a wetting surface for the remaining filling process.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 6268291 (2001-07-01), Andricacos et al.
patent: 6326301 (2001-12-01), Venkatesan et al.
patent: 6352926 (2002-03-01), Ding et al.
patent: 6372633 (2002-04-01), Maydan et al.
Cordasco Vincent T.
Hong Qi-Zhong
Hsu Wei-Yung
McLarty Peter K.
Perkins Pamela
Zarabian Amir
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