Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-12-12
2009-11-10
Kebede, Brook (Department: 2894)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S691000, C257SE21585
Reexamination Certificate
active
07615475
ABSTRACT:
A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilicon layer is doped with an impurity to provide conductive characteristics. The method forms a cap layer (e.g., silicon nitride, silicon oxynitride) overlying the polysilicon layer. The method forms an Al2O3layer using atomic layer deposition overlying the polysilicon layer to form a sandwich structure including the polysilicon layer, cap layer, and Al2O3layer. The method includes patterning the sandwich layer to form a plurality of gate structures. Each of the gate structures includes a portion of the polysilicon layer, a portion of the cap layer, and a portion of the Al2O3layer. The method forms an interlayer dielectric material (e.g., BPSG, FSG) having an upper surface overlying the plurality of gate structures. The method also includes patterning the interlayer dielectric material to form an opening in a portion of the interlayer dielectric material to expose each of the gate structures and filling the opening with a polysilicon fill material to a vicinity of the upper surface of the interlayer dielectric material. Preferably, the fill material is doped using an impurity. The method also performs a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer concurrently with a portion of the polysilicon fill material and maintains the chemical mechanical polishing process until a portion of the Al2O3layer overlying one of the gate structures has been exposed. The method uses portions of the Al2O3layer as a polish stop while preventing any exposure of any portion of the polysilicon layer.
REFERENCES:
patent: 7138340 (2006-11-01), Lee et al.
patent: 2005/0009280 (2005-01-01), Fishburn et al.
Senzaki et al., Atomic Layer Deposition of High-k Thin Films for Gate and Capacitor Dielectrics, IEEE, pp. 269-274, 2004.
Kebede Brook
Semiconductor Manufacturing International (Shanghai) Corporation
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