Method for fabricating isolation layer of semiconductor device

Details Method for fabricating isolation layer of semiconductor device Method for fabricating isolation layer of semiconductor device

1996-12-27

1998-05-05

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438439, 438444, 438445, 438452, H01L 2176

Patent

active

057473765

ABSTRACT:
A method for fabricating an isolation layer of a semiconductor device defines an active region and an isolation region on a semiconductor substrate. An active pattern is formed on the active region of the semiconductor substrate and the active pattern includes a first insulating layer and a first oxidation stop layer formed on the first insulating layer. A first isolation layer is grown over the substrate corresponding to the isolation region and the first isolation layer is selectively etched by using the first oxidation stop layer as a mask. A sidewall spacer is formed adjacent to the active pattern including a remaining portion of the first isolation layer, and the sidewall spacer includes a second insulating layer and a second oxidation stop layer formed on the second insulating layer. A second isolation layer is grown over the substrate.

REFERENCES:
patent: 5326715 (1994-07-01), Jang et al.
patent: 5554543 (1996-09-01), Yang
patent: 5567645 (1996-10-01), Ahn et al.
N. Shimizu et al., "A Poly-Buffer Recessed LOCOS Process for 256Mbit DRAM Cells", IEDM 92, pp. 279-282, Dec. 1992.

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