Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-06-03
1999-01-12
Chang, Joni
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438618, 438622, H01L 2144, H01L 214763
Patent
active
058588698
ABSTRACT:
A method for making multilevel electrical interconnections having a planar intermetal dielectric (IMD) with low dielectric constant k and good thermal conductivity was achieved. The method involves patterning an electrically conductive layer to form metal lines on which is deposited an anisotropic plasma oxide (APO) resulting in a thin oxide on the sidewalls of the metal lines and a much thicker oxide on top of the lines. A low dielectric constant (k) polymer is deposited and the polymer and APO are chem/mech polished back to the top of the metal lines. A fluorine-doped silicon oxide (FSG) is deposited, and via holes are etched to provide electrical connections for the next level of interconnections. The APO provides wider openings between metal lines filled with the low k dielectric polymer thereby reducing the RC time delay of the circuit. The thick top APO provides more processing latitude for polishing back the APO and low k polymer. The FSG provides a lower dielectric constant k for further reducing the RC delay and a better thermal conductivity constant K for minimizing the Joule heating when the circuit is powered up. The process can be repeated several times to form a planar multilevel interconnection for completing wiring on the integrated circuit.
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Chen Lai-Juh
Wang Chien-Mei
Ackerman Stephen B.
Chang Joni
Industrial Technology Research Institute
Saile George O.
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