Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-21
2001-05-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S669000, C438S739000, C438S221000, C438S282000, C438S422000, C438S778000
Reexamination Certificate
active
06232214
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106212, filed Apr. 19, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating an inter-metal dielectric layer. More particularly, the present invention relates to a method for fabricating an inter-metal dielectric layer, which reduces RC delay.
2. Description of the Related Art
Because the linewidth of devices is continuously shrinking, the parasitic capacitor effect between metal wires is increasingly serious and RC delay increases. The parasitic capacitor effect easily occurs because the dielectric constant of a dielectric material, which forms an inter-metal dielectric layer, is large. Dielectric material with a low dielectric constant is therefore chosen to overcome the above problem.
In conventional technology, however, the parasitic capacitor effect between metal wires is not always effectively decreased because the dielectric constant of the dielectric material is not low enough.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for fabricating an inter-metal dielectric layer, which reduces RC delay.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating an inter-metal dielectric layer. The method includes the following steps. Several conducting wires are formed on a substrate, with openings between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.
Because the spacer is formed on the sidewall of each of the conducting wires, the opening is narrower. A void is formed in the second dielectric layer. Since the dielectric constant of air is about 1, dielectric constant of a region between the narrower conducting wires is reduced. As a result, RC delay is reduced, and performance of the device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
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patent: 5953625 (1999-09-01), Bang
patent: 6035530 (2000-03-01), Hong
Hong Gary
Lee Claymens
Huang Jiawei
J.C. Patents
Rocchegiani Renzo N.
Smith Matthew
United Microelectronics Corp.
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