Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2000-02-25
2002-07-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000, C438S018000
Reexamination Certificate
active
06423558
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating semiconductor integrated circuit dies with multi-layered interconnect structures.
A semiconductor integrated circuit of a high integration level comprises a plurality of stacked interconnect layers to define a plurality of sub-circuits having a variety of functions after primitive devices have been formed.
In
FIG. 1
, there is shown a semiconductor integrated circuit having a plurality of sub-circuits. A semiconductor integrated circuit A shown has a plurality of sub-circuits S
1
, S
2
, . . . , Sk (k=6 in the example shown in FIG.
2
). Sub-circuits may be large scale functional blocks such as CPU, memory, DSP, AD converter, I/O interface or the like, or may be relatively small scale or basic sub-circuits such as adder, multiplier, multiplexer, flip-flop or the like. In addition , the functional blocks and sub-circuits may be digital circuits, analog circuits or mixed signal circuits.
The semiconductor integrated circuit A has a multi-layered interconnect structure comprising a plurality of interconnect layers (N-layers as shown in FIG.
2
). A lowermost layer (the first interconnect layer) provides a wiring connection between primitive devices (transistors) formed in a semiconductor substrate, and is the interconnect layer which defines a basic logic gate, which is an NAND gate or an inverter in the example shown, as shown in FIG.
3
. Input and output signal lines for the basic logic gates appear on the stacking surface of the first interconnect layer. Shown within blocks of this Figure which are indicated in broken lines are primitive devices, which do not appear on the surface of the first interconnect layer. The second interconnect layer provides a wiring connection between the basic logic gates which are formed by the first interconnect layer, and is the interconnect layer which defines relatively small scale sub-circuits as illustrated in
FIG. 4
, for example. Input and output signal lines for the sub-circuit appear on the surface of the second interconnect layer, but logic gates or inverters which constitute such circuits do not appear there. The i-th interconnect layer (
3
≦i≦N-
1
) provides a wiring connection between sub-circuits which have been formed up to the (i-
1
)-th interconnect layer, and is the interconnect layer which defines sub-circuits of a higher scale, and input and output signal lines for the sub-circuits of the higher scale appear on the stacking surface of the i-th interconnect layer. An uppermost layer (N-th interconnect layer) provides a wiring connection between sub-circuits (S
1
, S
2
, . . . , Sk) which are formed by the (N-
1
)-th interconnect layer, and is the interconnect layer which defines a semiconductor integrated circuit A. Only input and output signal lines for the semiconductor integrated circuit A appear on the stacking surface of the N-th interconnect layer, as shown in FIG.
5
.
Stacking of individual interconnect layers takes place in a manner shown in FIG.
6
. While not shown, a product from an immediately preceding step, namely a substrate in which primitive devices are formed or an immediately preceding interconnect layer is initially subject to a deposition thereon of an oxide layer
11
such as formed by SiO
2
, as shown in FIG.
6
(
a
).
Photolithography is applied to the oxide layer
11
to define a mask for junctions with wirings or primitive devices located directly below it, and then the reactive ion etching (RIE) technique is applied to form openings
12
, as shown in FIG.
6
(
b
). The openings
12
are then filled with a conductive material, for example, tungsten to form junctions (stubs)
13
, as shown in FIG.
6
(
c
). As shown in FIG.
6
(
d
), an oxide layer
14
as formed by SiO
2
deposition
Photolithography is applied to the oxide layer
14
to define mask and the reaction ion etching (RIE) technique is applied to form grooves
15
for regions to be wired, as indicated in FIG.
6
(
e
). A layer
16
of a metal such as Al, W, Cu or the like is formed as shown in FIG.
6
(
f
), and the metal layer
16
is then subject to a chemical-mechanical polishing (CMP) to expose the oxide layer
14
. Wires
17
which fill the grooves
15
form a wiring
17
which is connected to the junctions
13
and also connected to the underlying interconnect layer, not shown, through the junctions
13
.
Steps to stack an interconnect layer may follow a procedure shown in FIG.
7
. In a similar manner as illustrated in
FIG. 6
, a condition as shown in FIG.
7
(
a
) is prepared in which junctions
13
fill in an oxide layer
11
. Subsequently, a metal layer
16
is formed over the entire surface as shown in FIG.
7
(
b
), and the application of the photolithography and the RIE technique form wires
17
connected to the junctions
13
, as shown in FIG.
7
(
c
). An oxide layer
18
is then deposited over the entire surface as shown in FIG.
7
(
d
), and the surface of the oxide layer
18
is planarized by CMP, as shown in FIG.
7
(
e
). In this instance, when openings
12
are formed to provide the junctions
13
, the openings
12
should contiguously extend to reach the wires in the underlying interconnect layer.
A method for fabricating a semiconductor integrated circuit with a multi-layered interconnect structure has been briefly described above. In a conventional method for fabricating a semiconductor integrated circuit, there has been no practice of testing primitive devices or sub-circuits which have been already formed in the course of the fabricating steps.
In other words, a test of the semiconductor integrated circuit has taken place by placing a probe in contact with bonding pads of a chip as shown in
FIG. 8
after the steps of fabricating a semiconductor integrated circuit chip have been completed to provide an IC in a wafer condition, inputting externally a test pattern to input pads on the circuit under test, and observing a voltage response signal on a power supply pad of the circuit under test or a current response signal through a power supply pad of the circuit under test(wafer probing, die sort). Alternatively, a test pattern is externally input to an input terminal (pin) of the circuit under test and a voltage response signal on an output terminal (pin) of the circuit under test or a current response signal through a power supply terminal (pin) of the circuit under test is observed to perform a test of the semiconductor integrated circuit (package test or final test). Such tests will be hereafter referred to as final tests.
A final test of the semiconductor integrated circuit utilizes a stuck-at fault test, a delay fault test, a quiescent power supply current (IDDQ) test, a functional test, an exhaustive test and the like. The stuck-at fault test is a procedure which assumes a stuck-at fault on a signal line in the circuit under test (which is a fault where a logical signal value on the signal line is fixed to a certain value; a fault in which the signal value is fixed to “0” is referred to as stuck-at 0 fault while a fault in which the signal value is fixed to “1” is referred to as stuck-at 1 fault) by seeing an influence of a fault through the observation of a voltage signal on an output terminal of the circuit under test with respect to a given test pattern. The delay fault test is a procedure which assumes a delay fault in a signal propagation path or a logical gate in the circuit under test, or a fault that a time interval required for a signal to propagate through the signal propagation path or the logical gate (delay time) exceeds or undershoots a given value (a delay fault in the signal propagation path being referred to as a path delay fault and a delay fault in the logical gate as a gate delay fault), by seeing an influence of a fault through the observation of a voltage transition signal on an output terminal of the circuit under test with respect to a given series of test patterns. The quiescent power supply current test is a procedure which assumes a short-circuit fault across a plurality of signal lin
Ishida Masahiro
Maeda Yasuhiro
Soma Mani
Yamaguchi Takahiro
Advantest Corporation
Gallagher & Lathrop
Lathrop David N.
Lytle Craig P.
Smith Matthew
LandOfFree
Method for fabricating integrated circuit (IC) dies with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating integrated circuit (IC) dies with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating integrated circuit (IC) dies with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2859455