Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-12-18
2003-11-04
Chen, Jack S J (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S299000, C438S270000, C438S289000
Reexamination Certificate
active
06642130
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION This application claims the priority of Korean patent application Serial No.
2001-81786,
filed on Dec. 20, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a transistor in a semiconductor device, and more particularly to a method for fabricating a highly integrated transistor of a trench type.
2. Description of the Prior Art
As generally known in the art, a semiconductor integrated circuit device generally employs MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as unit transistors and integrates lots of unit transistors into one identical semiconductor substrate to embody an integrated circuit. The transistors as explained above have horizontal type structures, they rely more and more on lithography, and effective channels thereof are remarkably weakened following the increase of the degree of integration of semiconductor devices, resulting in the production of several problems as follows.
For example, as the channel of the transistor becomes shorter, there occurs a short channel effect in that threshold voltages decrease or a reverse channel effect in that threshold voltages increase, and a gate induced drain leakage (GIDL) phenomenon occurs in a semiconductor substrate using a thin gate oxide film.
Further, a punch through phenomenon increases, and when the transistor is not activated, leakage current (I
OFF
) increases, junction capacitance in a source/drain region increases, and change of the threshold voltage has occurred.
Meanwhile, various studies and developments have been performed in order to accomplish high current drivability, ultra high speed, and ultra low powers.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a highly integrated transistor for a semiconductor device that is capable of high integration and can improve electrical characteristics and reliability of the semiconductor device.
Another object of the present invention is to provide a transistor for a semiconductor device that has reduced production costs and time required for accomplishing the transistor.
In order to accomplish these objects, there is provided a method for fabricating a highly integrated transistor, comprising the steps of: forming a well region having a first conductive type on a silicon substrate; forming an isolation oxide layer on a desired region of a surface of the silicon substrate; forming a first pad oxide layer on the surface of the silicon substrate; forming a LDD (low doped drain) region and a source/drain region on an active region of the silicon substrate, wherein said LDD region and said source/drain region having a second conductive type; forming a pad nitride layer on the first pad oxide layer; forming a trench through sequential etching desired parts of the pad nitride layer, the first pad oxide layer, the source/drain region, and the LDD region to expose side surfaces of the source/drain region and the LDD region; forming a second pad oxide layer along the exposed side surfaces of the source/drain region, the LDD region and on a bottom of the trench; removing a portion of the second pad oxide layer formed at the bottom of the trench and portions of the LDD region and the upper part of the well region; forming a gate in the trench; forming an interlayer insulating layer on the surface of the silicon substrate including the gate; etching the interlayer insulating layer to form contact holes; and forming a source electrode, a drain electrode, and a gate electrode, each of which is electrically connected with the source/drain region and the gate.
In the present method, it is preferable that the etching of the trench-forming step be controlled so that the etching can be stopped at the inside of the LDD region, and furthermore, it is preferable that the etching be performed under a condition in which the etch selection rate of the source/drain region, the LDD region, and the first pad oxide layer with respect to the pad nitride layer is 1:1:1.
Also, it is preferable for the thickness of the second pad oxide layer formed on the respective surfaces of the source/drain region and the LDD region differ from one another, and the second pad oxide layer can be formed through a thermal oxidation process. Further, the step of removing the LDD region and the upper part of the well region and the second pad oxide layer formed at the bottom of the trench can be performed through an anisotropic dry etching.
Meanwhile, the method for fabricating such a transistor further comprises a step of forming a doped region for controlling the threshold voltage at the lower part of the trench prior to forming the gate, and the step of forming the doped region for controlling the threshold voltage can comprise steps of forming a sacrificial oxide layer, implanting ions, and removing the sacrificial oxide layer. Also, the step of forming the gate comprises the steps of depositing gate forming materials on the entire resultant structure in order to fill the trench, and performing planarization of the deposited gate forming materials.
The method for fabricating a highly integrated transistor may also comprise, after the step of forming the gate, a step of forming silicide layers on both the gate and the source/drain region by a self-alignment method, and may further comprise the step of removing the pad nitride layer prior to the forming the interlayer insulating layer.
REFERENCES:
patent: 6087706 (2000-07-01), Dawson et al.
patent: 6090661 (2000-07-01), Perng et al.
patent: 6150219 (2000-11-01), Tung
patent: 6309933 (2001-10-01), Li et al.
Chen Jack S J
Dongbu Electronics Co. Ltd.
Keefer Timothy J.
Wildman Harrold Allen & Dixon
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