Method for fabricating high-speed thin-film transistors

Details Method for fabricating high-speed thin-film transistors Method for fabricating high-speed thin-film transistors

2011-06-14

2011-06-14

Nguyen, Cuong Q (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S479000, C438S480000

Reexamination Certificate

active

07960218

ABSTRACT:
This invention provides methods for fabricating high speed TFTs from silicon-on-insulator and bulk single crystal semiconductor substrates, such as Si(100) and Si(110) substrates. The TFTs may be designed to have a maximum frequency of oscillation of 3 GHz, or better.

REFERENCES:
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4846931 (1989-07-01), Gmitter et al.
patent: 4883561 (1989-11-01), Gmitter et al.
patent: 4980308 (1990-12-01), Hayashi et al.
patent: 5051803 (1991-09-01), Kitamura et al.
patent: 5073230 (1991-12-01), Maracas et al.
patent: 5087585 (1992-02-01), Hayashi
patent: 5286670 (1994-02-01), Kang et al.
patent: 5344517 (1994-09-01), Houlding
patent: 5376559 (1994-12-01), Mukai et al.
patent: 5461243 (1995-10-01), Ek et al.
patent: 5465009 (1995-11-01), Drabik et al.
patent: 5528397 (1996-06-01), Zavracky et al.
patent: 5759898 (1998-06-01), Ek et al.
patent: 6018187 (2000-01-01), Theil et al.
patent: 6054734 (2000-04-01), Aozasa et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6214733 (2001-04-01), Sickmiller
patent: 6242762 (2001-06-01), Brown et al.
patent: 6410371 (2002-06-01), Yu et al.
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6602613 (2003-08-01), Fitzgerald
patent: 6603156 (2003-08-01), Rim
patent: 6703144 (2004-03-01), Fitzgerald
patent: 6713326 (2004-03-01), Cheng et al.
patent: 6756324 (2004-06-01), Gates
patent: 6765227 (2004-07-01), Yu et al.
patent: 6809358 (2004-10-01), Hsieh et al.
patent: 6812495 (2004-11-01), Wada et al.
patent: 6831263 (2004-12-01), Skurnik et al.
patent: 7038277 (2006-05-01), Chu et al.
patent: 7205204 (2007-04-01), Ogawa et al.
patent: 7354809 (2008-04-01), Yuan et al.
patent: 2001/0019371 (2001-09-01), Zavracky et al.
patent: 2002/0096717 (2002-07-01), Chu et al.
patent: 2002/0168864 (2002-11-01), Cheng et al.
patent: 2003/0124815 (2003-07-01), Henley et al.
patent: 2003/0168659 (2003-09-01), Lal et al.
patent: 2003/0222334 (2003-12-01), Ikeda et al.
patent: 2004/0146138 (2004-07-01), Jiao
patent: 2004/0217423 (2004-11-01), Park et al.
patent: 2004/0253792 (2004-12-01), Cohen et al.
patent: 2005/0054121 (2005-03-01), Handy et al.
patent: 2005/0082526 (2005-04-01), Bedell et al.
patent: 2005/0184354 (2005-08-01), Chu et al.
patent: 2005/0233493 (2005-10-01), Augusto
patent: 2005/0263774 (2005-12-01), Kim et al.
patent: 2006/0038182 (2006-02-01), Rogers et al.
patent: 2006/0134893 (2006-06-01), Savage et al.
patent: 2007/0187719 (2007-08-01), Yuan et al.
patent: 2008/0315253 (2008-12-01), Yuan et al.
patent: WO 2005/122285 (2005-12-01), None
U.S. Appl. No. 60/577,077, filed Feb. 23, 2006, Rogers et al.
U.S. Appl. No. 60/601,061, filed Feb. 23, 2006, Rogers et al.
U.S. Appl. No. 60/650,305, filed Feb. 23, 2006, Rogers et al.
U.S. Appl. No. 60/663,391, filed Feb. 23, 2006, Rogers et al.
U.S. Appl. No. 60/677,617, filed Feb. 23, 2006, Rogers et al.
Non Final Office Action received in U.S. Appl. No. 12/042,066, Sep. 2, 2009, pp. 1-11.
Final Office Action, received in U.S. Appl. No. 12/042,066, Mar. 10, 2010, pp. 1-14.
Advisory Action Before the Filing of an Appeal Brief, received in U.S. Appl. No. 12/042,066, May 19, 2010, pp. 1-2.
International Search Report received for PCT/US06/39831, Mar. 26, 2008.
G.K. Celler, Frontiers of Silicon-On-Insulator, Journal of Applied Physics, May 1, 2003, pp. 4955-4978, vol. 93-No. 9, American Institute of Physics, U.S.A.
A. Ikeda, Design and Measurements of Test Element Group Wafer Thinned to 10 am for 3d System in Package, Conference on Microelectronic Test Structures, Mar. 2004, pp. 161-164, vol. 17, IEEE, U.S.A.
Lei Xue et al, Three-Dimensional Integration: Technology, Use, and Issues for Mixed-Signal Applications, IEEE Transactions on Electron Devices, Mar. 2003, pp. 601-609, vol. 50-No. 3, IEEE, U.S.A.
E. Menard et al, A Printable form of silicon for high performance thin film transistors on plastic substrates, Appl. Phys. Lett., Jun. 17, 2004, pp. 5398-5400,vol. 84-No. 26, American Institute of Physics, U.S.A.
E. Menard et al, Bendable single crystal silicon thin film transistors formed by printing on plastic substrates, Appl. Phys. Lett., Feb. 25, 2005, pp. 093507-1-093507-3, vol. 86, American Institute of Physics, U.S.A.
Z.-T Zhu et al, Spin on dopants for high-performance single-crystal silicon transistors on flexible plastic substrates, Appl. Phys. Lett., Mar. 23, 2005, pp. 133507-1-133507-3, vol. 86, American Institute of Physics, U.S.A.
Yugang Sun et al, Bendable GaAs metal-semiconductor field-effect transistors formed with printed GaAs wire arrays on plastic substrates, Appl. Phys. Lett., Aug. 15, 2005, pp. 083501-1-083501-3, vol. 87, American Institute of Physics, U.S.A.
Seokwoo Jeon et al, Three-Dimensional Nanofabrication with Rubber Stamps and Conformable Photomasks, Adv. Mater., Aug. 4, 2004, pp. 1369-1373, vol. 16-No. 15, Wiley-VCH, Germany.
Yueh-Lin Loo et al, Soft, conformable electrical contacts for organic semiconductors: High-resolution plastic circuits by lamination, PNAS, Aug. 6, 2002, pp. 10252-10256, vol. 99-No. 16, PNAS, U.S.A.
Rafael Reif et al, Fabrication Technologies for Three-Dimensional Integrated Circuits, Proceedings of the International Symposium on Quality Electronic Design (ISQED'02), IEEE, Apr. 2002, IEEE.
Hao-Chih Yuan, Silicon-Based Nanomembrane Materials: The Ultimate in Strain Engineering, Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, sponsored by the IEEE Microwave Theory and Techniques Society, San Diego, CA, Jan. 18-20, 2006, pp. 327-333, IEEE.
Issac Lauer, Double-Sided CMOS Fabrication Technology, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Aug. 28, 2001, pp. 1-66, Massachusetts Institute of Technology, U.S.A.
Response to Final Office Action filed in U.S. Appl. No. 12/042,066, May 7, 2010.
Non-Final Office Action received in U.S. Appl. No. 12/877,269, Jan. 31, 2011.
U.S. Appl. No. 11/452,135, filed Jun. 13, 2006, Lagally et al.
J.F. Damlencourt, et al., “High-Quality Fully Relaxed In0.65Ga0.35As Layers Grown on InP Using the Paramorphic Approach,:” Applied Physics Letters, vol. 75, No. 23, Dec. 6, 1999, pp. 3638-3640.
Jean-Francois Damlencourt, et al., “Paramorphic Growth: A New Approach in Mismatched Heteroepitaxy to Prepare Fully Relaxed Materials,” Jpn. J. Appl. Phys., vol. 3, 1999, pp. L996-L999.
P.M. Mooney, et al., “Elastic Strain Relaxation in Free-Standing SiGe/Si Structures,” Applied Physics Letters, vol. 84, No. 7, Feb. 16, 2004, pp. 1093-1095.
E. Menard, et al., “A Printable Form of Silicon for High Performance Thin Film Transistors on Plastic Substrates,” vol. 84, No. 26, Jun. 28, 2004, pp. 5398-5400.
G.M. Cohen, et al., “Free Standing Silicon as a Compliant Substrate for SiGe,” CMOS Front-End Materials and Process Technology. Symposium. (Mater. Res. Soc. Symposium Proceedings vol. 765), 2003, p. 141-146.
Patricia M. Mooney, et al. “Defect-Free Strained Si-on-Insulator Fabricated from Free-Standing Si/SiGe Structures,” Abstract—2004 Materials Research Society Spring Meeting, Symposium B High-Mobility Group IV Materials and Devices.
P.M. Mooney, et al., “Strained Si-on-Insulator Fabricated from Elastically-Relaxed Si/SiGe Structures,” Mat. Res. Soc. Symp. Proc., vol. 809, 2004 Materials Research Society, pp. B1.3.1-B1.3.6.
G.M. Cohen, et al., “Free Standing Silicon as a Compliant Substrate for SiGe,” Mata Res. Soc. Symp. Proc., vol. 765, 2003 Materials Research Society, pp. D4.6.1/G1.6.1-D4.6.6/G1.6.6.
Mouloud Boudaa, et al., “Growth and Characterization of Totally Relaxed InGaAs Thick Layers on Strain-Relaxed Paramorphic InP Substrates,” Journal of Electronic Materials, vol. 33, No. 7, 2004, pp. 833-839.
Y.H. Lo, “New Approach to Grow Pseudomorphic Structures Over the Critical Thickness,” Appl. Phys. Lett., vol. 59, No. 18, Oct. 28, 1991, pp. 2311-2313.
F.E. Ejeckam, et al., “Lattice Engineered Compliant Substrate for Defect-Free Heteroepitaxial Growth,” Appl. Phys. Lett., v

Affiliated with

Also associated with

Rating

Method for fabricating high-speed thin-film transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating high-speed thin-film transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating high-speed thin-film transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2665447