Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-08-05
2003-06-24
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S949000, C430S318000, C430S319000
Reexamination Certificate
active
06583037
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a gate of semiconductor device and, more particularly, to a method for fabricating a gate of semiconductor device capable of preventing generation of critical dimension CD difference between pattern densed region and isolated region.
2. Description of the Related Art
As a semiconductor device is highly integrated, line width of a gate becomes reduced with the cell size. Therefore, research and efforts are focused on development of gate realizing low resistance with fine line width.
Generally, polysilicon has been widely employed as a gate material, which has limitations in realizing low resistance on the gate having fine line width. Therefore, polycide gate has been proposed to realize low resistance with fine line width and recently, research is in progress on the development of metal gate.
The polycide gate or metal gate has been obtained by a conventional art including the following steps.
A gate oxide layer and a gate material layer are sequentially formed on a semiconductor substrate, wherein the gate material layer is a stacked layer comprising a polysilicon layer and a metal silicide layer or a stacked layer comprising a polysilicon layer, a barrier layer and a metal layer. A mask oxide layer is formed on the gate material layer.
A photoresist pattern is formed on the mask oxide layer via coating, exposure and development procedures to define a gate formation region. The mask oxide layer is etched in a shape of resist pattern.
Then, the residual photoresist pattern is removed. The gate material layer and the gate oxide layer are etched in accordance with a RIE (Reaction Ion Etching) process using the etched mask oxide layer as an etch barrier, thereby forming a polycide or a metal gate realizing low resistance with fine line width.
However, in the conventional method, there is a problem that pattern CD difference is generated between densed region and isolated region, for example, cell region and peripheral circuit region, as shown in
FIG. 1
, thereby deteriorating device properties and lowering the yield rate. In
FIG. 1
, a reference number
1
is a semiconductor substrate,
2
is a gate oxide layer,
3
is a gate material layer,
4
is a mask oxide layer and
10
is a polycide or a metal gate.
That is, the polycide or the metal gate is formed by dry etching the gate material layer using the mask oxide layer as an etch barrier, wherein the mask oxide layer as an etch barrier is etched in a shape of photoresist pattern obtained via photoresist coating, exposure and development procedures.
However, the photoresist pattern may have different CD between cell region and peripheral circuit region due to proximity effect by pattern density during the exposure process.
In this case, the mask oxide layer is etched in a shape of photoresist pattern having CD difference between the regions and therefore, the etched mask oxide layer also has CD difference between the regions. And, the gate material layer is etched by using the mask oxide layer having CD difference as an etch barrier and therefore, the polycide or metal gate also has CD difference between cell region and peripheral circuit region.
As a result, the conventional method has generated CD difference between pattern densed region and isolated region, thereby deteriorating device properties and lowering the yield rate.
To overcome the generation of CD difference between densed region and isolated region, several methods have been proposed including device modification and change of parameter. However, the conventional method has limitations in preventing the CD difference.
SUMMARY OF THE INVENTION
Accordingly, it is the primary objective of the invention to provide a method for fabricating a gate of semiconductor device preventing generation of CD difference between pattern densed region and isolated region.
To accomplish the object, the present invention comprises the steps of: sequentially forming a gate oxide layer, a gate material layer and a mask oxide layer on a semiconductor substrate; coating photopolymer on the mask oxide layer, wherein the photopolymer has compound accelerator including polar functional group which absorbs HF vapor and ionizes at a predetermined high temperature; exposing the photopolymer and crosslinking the portion of exposed photopolymer; performing DFVP process by passing over HF vapor on the resultant substrate at a predetermined high temperature, thereby developing the portion of exposed photopolymer and etching the portion of mask oxide layer exposed by the developed photopolymer, simultaneously; removing the residual photopolymer; and etching the gate material layer and the gate oxide layer using the etched mask oxide layer.
According to the present invention, the photopolymer is a cinnamate type including 5-nitroacenaphthene, described by the following structural formula.
And, the DFVP process is performed at a high temperature over 100° C.
REFERENCES:
patent: 5824596 (1998-10-01), Naem
patent: 6207541 (2001-03-01), Das et al.
patent: 6326290 (2001-12-01), Chiu
patent: 6387787 (2002-05-01), Mancini et al.
patent: 03-276627 (1991-12-01), None
Cho Sung-Yoon
Jun Bum-Jin
Booth Richard
Hynix / Semiconductor Inc.
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