Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1999-02-18
1999-09-07
Fahmy, Wael M.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438404, 438405, 438408, 438424, 438433, 438960, 148DIG50, H01L 2176
Patent
active
059500948
ABSTRACT:
The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions. Ion species can optionally be implanted into the sidewalls of the isolated silicon regions to form lightly doped regions to act as channel stops. A fill oxide layer is deposited over the buried oxide layer and the liner oxide layer. The fill oxide layer and the liner oxide layer are removed down to the level of the top of the isolated silicon regions thereby exposing a fully dielectric isolated silicon.
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Chang Hui-Hua
Chen Yen-Ming
Lin Shih-Chi
Yu Hui-ju
Ackerman Stephen B.
Fahmy Wael M.
Pham Long
Saile George O.
Stoffel William J.
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