Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-27
2001-08-07
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S510000
Reexamination Certificate
active
06271561
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture, and more particularly to an improved method for fabricating floating gate semiconductor devices with trench isolation structures and self aligned floating gates. The method is particularly suited to the formation of non-volatile read only memories, such as flash EEPROMs.
BACKGROUND OF THE INVENTION
Semiconductor memory arrays can be fabricated using floating gates (i.e., unconnected gates) that control current flow through the devices of the array. One type of floating gate device used to construct memory arrays is referred to as a flash EEPROM (electrically erasable programmable read only memory).
A flash EEPROM memory array includes multiple cells that can be erased using a single erasing operation. Typically, a flash EEPROM cell includes a floating gate, that controls current flow through a channel region of a field effect transistor (FET). The floating gate is separated from a source and drain of the FET by a thin gate oxide layer. The flash EEPROM cell also includes an elongated control gate located in a direction transverse to the source and drain of the FET. The control gates can be the word lines, and the sources and drains of the FETs can be the bit lines of the memory array.
In operation of the flash EEPROM cell, the presence of electrons in the floating gate alters the normal operation of the FET, and the flow of electrons between the source and drain of the FET. Programming of the flash EEPROM can be accomplished by hot-electron injection into the floating gate. With one type of EEPROM cell, the erasing mechanism can be electron tunneling off the floating gate to the substrate. In a memory array with this type of EEPROM cell, the individual cells are electrically isolated from one another such that the individual cells can be selectively erased.
Conventional floating gate arrays, such as flash EEPROM arrays, utilize a thermally grown field oxide (FOX) to electrically isolate adjacent cells in the array. One problem with a thermally grown field oxide is that the surface of the field oxide has a non-planar topography. With a non-planar topography, the size and spacing of features on subsequently deposited and patterned layers, such as interconnect layers, is limited by the depth of focus of conventional photolithography exposure tools. This limits the feature sizes of the array.
Another problem with field oxide isolation is that the source and drain regions of the FETs of the array can be degraded due to exposure to temperature cycles during growth of the field oxide. This can cause the source and drain regions to become less efficient in the generation of hot electrons for injection through the gate oxide layer into the floating gate.
Another consideration in the formation of floating gate devices is the alignment of the floating gates relative to other elements of the device. For example, one type of flash EEPROM cell has a floating gate which extends across the channel region of an FET. Alignment of the floating gate to the channel region requires a critical alignment step. Consequently the floating gates of flash EEPROMs have sometimes been made larger than necessary to insure alignment of the floating gates with the channel regions. In addition to alignment, a thickness of the floating gates is a critical dimension that can affect capacitive coupling between the floating gates and the control gates of flash EEPROMs. In the past the thickness of the floating gates has been difficult to control, and the floating gates have been made thicker than necessary.
The present invention is directed to a method for fabricating floating gate devices in which trench isolation, such as shallow trench isolation (STI), rather than a thermally grown field oxide, is used to electrically isolate adjacent cells. In addition, the method employs chemical mechanical planarization (CMP) to self align the floating gates relative to other elements of the devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for fabricating a floating gate semiconductor device, and an improved floating gate semiconductor device, are provided. In an illustrative embodiment the method is used to fabricate a flash EEPROM cell, and a flash EEPROM memory array.
The method, simply stated, comprises: providing a semiconductor substrate; forming active areas in the substrate; forming trench isolation structures on the substrate for isolating the active areas; forming a gate dielectric layer on the active areas; forming floating gates on the gate dielectric layer by chemically mechanically planarizing a blanket deposited conductive layer to an endpoint of the trench isolation structures; and then forming a control gate dielectric layer and control gates on the floating gates.
Initially, a semiconductor substrate (e.g., silicon) can be provided and active areas formed in the substrate. Each active area can include elements of a field effect transistor (e.g., source, drain, channel region). Following formation of the active areas, a sacrificial oxide layer, and a mask layer, can be formed on the substrate. The mask layer can then be patterned using a resist mask, to form a hard mask, which can be used to etch isolation trenches in the substrate.
Next, a trench fill material, such as SiO
2
, can be deposited into the isolation trenches to form electrically insulating plugs. Following formation, the trench fill material can be removed to an endpoint of the mask layer preferably using chemical mechanical planarization (CMP). The mask layer can then be removed, leaving the trench fill material in each trench. With the mask layer removed, the trench fill material within each trench is higher than a surface of the substrate, such that recesses are formed which at least partially enclose each active area.
Following formation of the trench isolation structures, a gate dielectric layer can be formed on the active areas. In addition, a first conductive layer can be blanket deposited on the gate dielectric layer and partially removed and planarized preferably using CMP, to an endpoint of the trench fill material. The planarized conductive layer partially defines floating gates on the gate dielectric layer which are self aligned to the active areas. Next, a control gate dielectric layer can be deposited on the floating gates and on the trench fill material. A second conductive layer can then be deposited on the control gate dielectric layer and patterned to form control gates. During patterning of the second conductive layer, the planarized conductive layer can also be patterned to complete the floating gates.
The completed memory array includes rows and columns of flash EEPROM cells. Each flash EEPROM cell includes a FET with a source and drain, a gate dielectric layer on the source and drain, a self aligned floating gate on the gate dielectric layer, a control gate dielectric layer on the floating gate, and a control gate on the control gate dielectric layer. Trench isolation structures electrically isolate adjacent cells, and the floating gates of adjacent cells. In addition, the sources and drains of the FETs form the bit lines of the memory array, and the control gates form the word lines of the memory array.
Alternately the control gate dielectric layer can be deposited on the conductive layer prior to the chemical mechanical planarization step. The chemical mechanical planarization step can then be performed to planarize the control gate dielectric layer and the conductive layer.
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Booth Richard
Gratton Stephen A.
Micro)n Technology, Inc.
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