Method for fabricating ferroelectric memory cells

Details Method for fabricating ferroelectric memory cells Method for fabricating ferroelectric memory cells

2003-09-23

2004-10-19

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

06806097

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating memory cells in accordance with the stacked principle, in which a bonding layer immediately above the plug is formed between a lower capacitor electrode of a ferroelectric storage capacitor and a conductive plug of polysilicon which is formed beneath the ferroelectric storage capacitor and is used to electrically connect the capacitor electrode to a transistor electrode of a selection transistor formed in or on a semiconductor wafer. An oxygen diffusion barrier is formed above the bonding layer, and after the ferroelectric has been deposited it is subjected to a rapid thermal processing step in an oxygen atmosphere after the formation of the ferroelectric and before a ferro anneal thereof.
In the case of ferroelectric memory cells constructed according to the stacked cell principle, it is typical for transistors to be fabricated in or on a semiconductor wafer. Then, an intermediate oxide is deposited. The ferroelectric capacitor modules are fabricated on the intermediate oxide. The ferroelectric capacitor modules are connected to the transistors by a plug, which in the case of the stacked cell principle is located directly beneath the capacitor module.
To condition the ferroelectric layer of the ferroelectric capacitor module, it is necessary to carry out a ferro anneal in an oxygen atmosphere at temperatures of up to 800° C. During the ferro anneal, the plug, which generally is formed of polysilicon or tungsten, has to be protected from oxidation, since otherwise the electrical connection between the lower capacitor electrode and the transistor is irreversibly broken. Moreover, reactions between the electrodes, the ferroelectric and the plug is to be avoided wherever they adversely affect the functionality of the chip.
All products that are currently commercially available with ferroelectric layers are constructed according to the offset cell principle and have an integration density of only a few kilobits up to one megabit.
To protect the plug from oxidation in a ferroelectric memory constructed according to the stacked cell principle, layer systems that contain an oxygen diffusion barrier and a bonding layer below have been introduced. However, it is very difficult to prevent the oxidation of the oxygen diffusion barrier and in particular of the bonding layer below and of the plug of polysilicon or tungsten or its surface from the side during the ferro anneal.
Experiments carried out by the inventors on prototypes have shown that competing processes were taking place in the bonding layer consisting of titanium during the ferro anneal.
FIG. 1
shows a diagrammatic cross section through part of a ferroelectric memory cell constructed in accordance with the stacked cell principle.
FIG. 1
shows a plug
1
, which leads through an intermediate oxide layer
7
(TEOS) and is made, for example, from polysilicon, a lower part
2
of a bonding layer, for example made from TiSi
2
, located immediately above it, an upper part
3
of the bonding layer, for example made from Ti, located above the lower part of the bonding layer, a lower part
4
of an oxygen diffusion barrier, for example made from Ir, and above this a second part
5
of the oxygen diffusion barrier, for example made from IrO
2
. Above the upper IrO
2
section
5
of the oxygen diffusion barrier is the lower capacitor electrode
6
, for example consisting of Pt. The oxidation which takes place from the side during the ferro anneal is indicated by bold arrows filled in black in
FIG. 1
, and the simultaneous formation of TiSi—Ir in the bonding layer
2
,
3
is denoted by unfilled arrows in
FIG. 1. A
circle denoted by II surrounds an excerpt, details of which are illustrated in
FIGS. 2A and 2B
, to which the description below relates. The processes and formations diagrammatically depicted in
FIGS. 2A and 2B
result from transmission electron microscope (TEM) images produced by the inventors.
FIG. 2A
once again uses a bold arrow to show the oxidation of the bonding layer
2
,
3
which takes place from the side. In this case, an insulating TiSi—O region
10
forms from the side. The arrows that are not colored in in black illustrate the siliciding, namely the formation of TiSi—Ir, which takes place from above and below. In
FIG. 2A
, the conductive TiSi—Ir layer has taken place more quickly than the formation of the insulating TiSi—O layer
10
from the side.
By contrast, in
FIG. 2B
the insulating TiSi—O region
10
from the side has formed over the entire width of the plug
1
, and the latter is no longer electrically connected to the lower electrode
6
of the ferroelectric capacitor.
It is therefore found that, despite the Ir/IrOx coverage of the Ti bonding layer, there is an oxygen diffusion path along the IrOx/TEOS interface, which can partly oxidize the bonding layer
2
.
During the experiments carried out by the inventors, it has emerged that the rate at which the formation of TiSi—O proceeds from the side and at which the simultaneous formation of TiSi—Ir from above and below takes place are dependent on the temperature at which these reactions occur.
With the aid of a rapid thermal processing (RTP) step in oxygen, it is possible to accelerate the formation of TiSi—Ir from above and below in the bonding layer compared to the formation of TiSi—O from the side.
A reference by M. Heintze, A. Catana, P. E. Schmid, F. Lévy, P. Stadelmann and P. Weiss, titled “Oxygen Impurity Effects On The Formation Of Thin Titanium Silicide Films By Rapid Thermal Annealing”, J. Phys. D: Appl. Phys., Bd. 23, 1990, pages 1076-1081, XP001124373, deals with the behavior of oxygen impurities in the diffusion between titanium and silicon during an RTP step in a temperature range from 480° C. to 800° C. By way of example,
FIG. 1
of the document shows concentration profiles of sintered Ti/Si diffusion pairs in the case of an RTP step at 500° C. for 20 seconds, 60 seconds and 120 seconds. Furthermore,
FIG. 2
of that document shows concentration profiles of titanium silicide specimens that have been treated by an RTP step for 60 seconds at 550° C., 600° C. and 800° C. On the basis of their tests, the editors come to the conclusion that the oxygen prevents the complete reaction of the siliciding of titanium at temperatures below 650° C. By contrast, above this temperature it is observed that titanium is completely consumed by the Ti/Si reaction and that the silicide that results is substantially free of oxygen contamination (FIG. 2C). The discoveries obtained in this document through tests therefore concur with the findings described by the present inventors in the introductory part of the description of the present patent application on the basis of
FIGS. 1
,
2
A and
2
B that the rate at which the formation of TiSi—O and the simultaneous formation of TiSi—Ir take place is dependent on the temperature at which these reactions take place, and that with the aid of an RTP step at high temperature it is possible to accelerate the formation of TiSi—Ir compared to the formation of oxide. However, the editors of the above-mentioned document do not give any indication whatsoever of calculating an optimum temperature range, and apart from the detail that the thickness of the Ti/Si specimen is 40 nm, their explanations do not give any statements concerning the influencing of the siliciding reaction as a function of the dimensions of a component.
Virtually identical results are obtained in the reference by Wee A T S, Huan A C H, Thian W H, Tan K L, Hogan R, titled “Investigation of Titanium Silicide formation using secondary Ion mass spectrometry”, Mat. Res. Soc. Symp. Proc., Vol. 342, 1994. The rapid high-temperature treatment referred to in that document as RTA (rapid thermal annealing) takes place for twenty seconds in a nitrogen atmosphere at approximately 650° C. Therefore, the rapid high-temperature treatment of that document differs from the RTP treatment in the present patent application, which takes place in an oxygen atmosphere. FI

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