Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2000-06-07
2001-09-18
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S945000
Reexamination Certificate
active
06291251
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a nonvolatile ferroelectric memory.
2. Background of the Related Art
FeRAM(Ferroelectric Random Access Memory) of a ferroelectric film has been widely studied as a memory which can replace nonvolatile memories, such as current flash memory, because, in general, the FeRAM not only has advantages of a fast writing speed, a low voltage driving, and a low power consumption, but also has a nonvolatile characteristic. In the current ferroelectric memories, there are ones with pairs of transistor and capacitor(1 transistor/1 capacitor type, 2 transistor/2 capacitor type), and ones with the ferroelectric film on a gate to form one transistor(1 transistor type). Researches for the ferroelectric memory is mostly focused on the 1 transistor/1 capacitor type.
In the meantime, recently a new type of SWL(Split Word Line) ferroelectric memory has been suggested, of which structure is as follows.
FIG. 1A
illustrates a circuit of a related art ferroelectric memory cell, and
FIG. 1B
illustrates a circuit of a related art SWL ferroelectric memory cell.
Referring to
FIGS. 1A and 1B
, though the SWL ferroelectric memory has no plateline of the related art ferroelectric memory, the SWL ferroelectric memory has the SWL adapted to serve as a wordline as well as a plateline of an adjacent cell. That is, different from the related art ferroelectric memory in which the platelines are electrically connected to a common line, since the SWL, ferroelectric memory has the SWL, serving as the plateline, not connected in common, the SWL feitoelectric memory is operative at a fast speed, and prevents degradation of unselected cells during writing/reading operation of selected cells. As shown in
FIG. 1B
, the SWL ferroelectric memory has the wordline connected to a lower electrode of the capacitor in an adjacent cell, to form the SW
1
. wordline. Therefore, it is favorable that the ferroelectric capacitor is formed on the wordline for fabricating a ferroelectric memory with a high device packing density. In this instance, the wordline and the lower electrode is electrically connected either directly by a conducting barrier formed between the wordline and the lower electrode, or by a metal interconnection in a contact hole formed between the lower electrode and the wordline.
FIG. 2
illustrates a section of the SWL ferroelectric memory, of which fabrication process is similar to a fabrication process of the related art ferroelectric memory.
First, a gate oxide(SiO
2
) layer and a polysilicon(Poly-Si) layer are formed over a substrate having a field oxide formed therein, and patterned, to form a wordline, and source/drain regions are formed on both sides of the wordline. Then, after an insulating layer is formed on an entire surface, a lower electrode, a ferroelectric layer, and an upper electrode are formed in succession on the insulating layer on the wordline, and patterned, to form a ferroelectric capacitor.
However, the related art method for fabricating the SWL ferroelectric memory has the following problem. The alignment allowance required between the wordline and the ferroelectric memory is not favorable for fabrication of a memory with a high device packing density and requires many fabrication process steps.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a nonvolatile ferroelectric memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a nonvolatile ferroelectric memory, which has a simple fabrication process and permits to minimize an alignment allowance.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating a nonvolatile ferroelectric memory, includes the steps of (1 ) forming an insulating layer, a semiconductor layer, an etch stop layer, a lower electrode, a ferroelectric layer, and an upper electrode on a substrate in succession, (2) forming an etch mask pattern of a required form on the upper electrode, (3) using the etch mask pattern as a mask in subjecting the upper electrode, the ferroelectric layer, the lower electrode, the etch stop layer, the semiconductor layer, and the insulating layer to en bloc etching, to expose the substrate, and (4) removing the etch mask pattern, and forming source/drain regions in the exposed substrate.
If the etch stop layer is formed of TiO
2
, the etch mask is formed of Ti, and if the etch stop layer is formed of RuO
2
, the etch mask is formed of Ru or Cr.
An etch gas for the etch mask of Ti is Cl
2
/N
2
, an etch gas for the etch mask of Ru or Cr is Cl
2
/O
2
, an etch gas for the etch stop layer of TiO
2
is C
2
F
6
(C
3
F
8
or CHF
3
)/Ar, and an etch gas for the etch stop layer of RuO
2
is Cl
2
/O
2
.
And, when the etch stop layer is formed of TiO
2
, the upper electrode, the ferroelectric layer and the lower electrode arc en bloc etched by Cl
2
/O
2
gas, and, when the etch stop layer is formed of RuO
2
, the upper electrode, the ferroelectric layer, and the lower electrode are etched by Cl
2
, Cl
2
/CF
4
, and Cl
2
gases, respectively.
The foregoing method for fabricating an SWL ferroelectric memory can simplify the fabrication process and minimize an alignment allowance, permitting to fabricate a memory with a high device packing density.
The introduction of the etch stop layer permits to prevent over etching of the wordline and the substrate.
And, the en bloc etching by using the etch stop layer and the metal mask is applicable to fabrication of the
1
transistor type ferroelectric memory of an MFMIS or MFIS structure with easy.
In other aspect of the present invention, there is provided a method for fabricating a nonvolatile ferroelectric memory, including the steps of (1) forming an etch stop layer, a ferroelectric layer, and an electrode layer on a substrate, (2) forming an etch mask pattern of a required form on the electrode layer, (3) using the etch mask pattern as a mask in subjecting the electrode layer, the ferroelectric layer, and the etch stop layer to en bloc etching, to expose the substrate, and (4) removing the etch mask pattern, and forming source/drain regions in the exposed substrate.
In this case too, if the etch stop layer is formed of TiO
2
, the etch mask is formed of Ti, and, if the etch stop layer is formed of RuO
2
, a gate oxide film is provided between the etch stop layer and the silicon, the etch mask is formed of Ru or Cr, and the same etch gas is used.
The foregoing method simplifies fabrication of an
1
transistor type ferroelectric memory of MFMIS or MFIS structure.
Since both the lower electrode and the etch stop layer are formed of RuO
2
, and both the insulating layer and the etch stop layer arc formed of TiO
2
, over etching of the substrate can be prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5989927 (1999-11-01), Yamanobe
patent: 6114228 (2000-09-01), Gardner et al.
Fleshner & Kim LLP
LG Electronics Inc.
Tsai Jey
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