Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-05-29
2003-05-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S016000, C438S758000
Reexamination Certificate
active
06569693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
A present invention relates to a method for fabricating a multilayer epitaxial substrate used for high speed electronic devices, in particular, for field effect transistors or integrated circuits including field effect transistors.
2. Description of the Related Art
The field effect transistor (FET) is a three-terminal device where an electron stream flowing between two terminals (source and drain) is controlled with the effect of an electric field applied to a gate electrode provided midway between the two terminals as the name implies. This is a type of transistor currently in widespread use as various amplifiers and switching elements particularly with a material made of GaAs or Si. GaAs is widely used especially in the high-frequency field due to its high electron velocity and excellent insulating characteristic and low dielectric loss characteristic in view of its high substrate resistance. These characteristics can be further improved by using a multilayer hetero-epitaxial substrate.
For example, one type of heterojunction FET called a pseudomorphic high electron mobility transistor (p-HEMT) includes an InGaAs layer and electron supply layers such as AlGaAs layers formed near the InGaAs layer. Electrons injected from a source electrode pass through layers including the electron supply layer vertically to enter the InGaAs layer having higher electron affinity and flow inside the InGaAs layer along an electric field formed in the drain direction. The current density is determined by the product of the electron density and the electron velocity.
In the heterojunction FET, the density and velocity of electrons flowing in the InGaAs layer are determined by the concentration and distribution of a donor impurity added to the n-type AlGaAs layers formed on both (upper and lower) sides of the InGaAs layer, the electric field applied to the gate, and the like. The heterojunction FET has superior device characteristics to those of general FETs due to the following reasons.
First, electrons flow in the InGaAs layer that has high electron velocity in a high electric field. Second, the donor impurity that will be a large cause of scattering of electrons is added only to the n-type AlGaAs layers and thus spatially separated from the InGaAs layer in which the electrons actually run. Third, the AlGaAs layer, having a large energy gap, is interposed between the gate electrode and the electron running layer. Therefore, leak current from the gate to the electron running layer, which will otherwise cause deterioration of FET characteristics, is not easily generated. This enables operation in a high electric field.
In fabrication of such a heterostructure FET, in order to maximize the characteristics described above, importance must be placed in particular, on the design and control of the extra-thin crystal layers, such as the n-type AlGaAs layers on the upper and lower sides of the InGaAs layer.
For example, in the p-HEMT, a typical type of heterojunction FET presently used, control of the threshold voltage (V
th
) is an important device parameters related to the crystal structure by the following Expression 1:
[Expression 1]
V
th
=&phgr;−&Dgr;E
c
−qNd
2
/2&egr;&egr;∘ (1)
(where V
th
: threshold voltage (V)
&phgr;: surface energy barrier height of the gate electrode portion (eV)
&Dgr;E
c
: energy difference at the bottom ends of the conduction bands of AlGaAs and InGaAs (eV)
q: charge elementary quantity (C)
N: donor concentration of the electron supply layer
d: thickness of the electron supply layer
&egr;&egr;∘: dielectric constant)
The above expression is for a p-HEMT having a simple structure composed of a single uniformly-doped electron supply layer and an InGaAs layer formed in contact with the electron supply layer. In many cases, actual crystals have multilayer junctions including numerous layers having different doping concentrations, compositions, and thicknesses in order to improve gate breakdown voltage and control of the channel electron density. It is therefore difficult to adopt the simplified expression as described above for actual devices.
In reality, therefore, the following technique has been adopted. An epitaxial substrate is first designed using appropriate values for the doping concentration, composition, and thickness of each epitaxial layer, which are important as design parameters. Various epitaxial substrates are fabricated by varying the above-mentioned design parameters of doping concentration, composition, and epitaxial layer thickness, and then devices are actually fabricated using such epitaxial substrates. The characteristics of the resultant devices are measured, to determine an epitaxial layer structure satisfying predetermined characteristics. Conventional device processing, however, generally requires a long time. In the conventional technique, it takes an extremely long time to determine the structure.
In addition, in the epitaxy process, problem arises in relation to the control of parameter such as the thickness, doping concentration, and composition of each layer, all of which are important for fabrication of the multilayer epitaxial substrate. Since the epitaxial layers are very thin, it is difficult to directly measure these values. Therefore, thick films are separately prototyped to enable direct measurement of the parameter values under the same conditions as those adopted in the fabrication of the multilayer epitaxial substrate. The thickness, doping concentration and composition of each layer are thus confirmed using these thick films before the multilayer epitaxial substrate is actually fabricated.
It will be appreciated that the conventional technique requires a considerably long time for feedback. Moreover, the conventional technique is disadvantageous in some cases when it is applied to various heterojunction FETs.
For example, it is known that, in the case of a very high concentration impurity doping, the impurity is activated to enable effective doping when the epitaxial layer is very thin, thin enough to be usable for the heterojunction crystal, but it is significantly inactivated when the epitaxial layer is thick (Y. Sasajima, M. Hata, Applied Physics Letters, 75, 2596(1999)). Thus, in this case, preliminary confirmation of the parameters using thick films is impossible.
In the p-HEMT, the InGaAs channel layer itself may sometimes be doped with an impurity to increase the electron concentration of the channel layer. Normally, the InGaAs channel layer of the p-HEMT is a very thin film having a thickness of several tens of nanometers or less to avoid occurrence of so-called “lattice relaxation”. When preliminarily measurement of the impurity concentration of the channel layer using a thick film as described above is attempted, a number of misfit dislocations are generated in the crystal of the thick film due to lattice relaxation. This influences the effective impurity concentration, making it virtually impossible to evaluate the impurity concentration.
The object of the present invention is to provide a method for fabricating a compound semiconductor multilayer epitaxial substrate that can substantially reduce the fabrication processes and also can be used to manufacture a multilayer epitaxial substrate having a unique structure for which conventional techniques cannot be utilized.
SUMMARY OF THE INVENTION
The present inventors have vigorously examined the above problems and invented a method for solving the above problems.
That is, the present invention is directed to a method for fabricating a compound semiconductor multilayer epitaxial substrate by determining one or more of the thicknesses, impurity concentrations, and compositions of epitaxial layers constituting the multilayer epitaxial substrate by theoretical calculation so that predetermined electric characteristics are satisfied, and performing epitaxy according to the determined values.
Additionally, the present invention is directed to a method for fabricating a compoun
Hata Masahiko
Zempo Yasunari
Birch & Stewart Kolasch & Birch, LLP
Luk Olivia T
Sumitomo Chemical Company Limited
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