Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-07-30
2003-07-15
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S582000, C438S583000, C438S592000, C438S648000, C438S649000, C438S655000, C438S656000, C438S664000, C438S682000, C438S683000
Reexamination Certificate
active
06593219
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating an electrode structure including a lower film of polysilicon or amorphous silicon and an upper film of a metal with a high melting point, and a method for fabricating a semiconductor device including the electrode structure as a gate electrode.
In a conventional MOS transistor, the gate electrode is formed from a polysilicon film. In accordance with refinement and increase in operation speed of LSIS, there are increasing demands for lowering resistance of a gate electrode of a MOS transistor.
For the purpose of lowering the resistance of a gate electrode, technique to use, as a gate electrode, a polymetal gate electrode of a multi-layer film including a lower polysilicon film and an upper metal film with a high melting point is proposed, and a tungsten film is proposed for use as the upper metal film with a high melting point. When a tungsten film is used as the upper metal film with a high melting point, the resistance of the gate electrode can be lowered.
It is necessary to form, between the polysilicon film and the tungsten film, a barrier film of tungsten nitride (WN,) or titanium nitride (TiN) for preventing a dopant (such as B, P and As) introduced into the polysilicon film from diffusing into the tungsten film (as described in, for example, Japanese Laid-Open Patent Publication Nos. 11-261059 and 7-235542).
FIG. 8A
shows the cross-sectional structure of an electrode structure according to a first conventional example. As shown in
FIG. 8A
, a gate electrode is formed above a semiconductor substrate
1
with a gate insulating film
2
sandwiched therebetween, and the gate electrode is composed of a polysilicon film
3
, a barrier film
4
A of tungsten nitride (WN
x
) and a tungsten film
5
successively formed in this order in the upward direction.
FIG. 8B
shows the cross-sectional structure of an electrode structure according to a second conventional example. As shown in
FIG. 8B
, a gate electrode is formed above a semiconductor substrate
1
with a gate insulating film
2
sandwiched therebetween, and the gate electrode is composed of a polysilicon film
3
, a barrier film
4
B of titanium nitride (TiN) and a tungsten film
5
successively formed in this order in the upward direction.
In the electrode structure of the first conventional example, when annealing is carried out in a subsequent procedure, nitrogen included in the barrier film
4
A of tungsten nitride is evaporated, so that the barrier film
4
A can be changed into the tungsten film
5
. In addition, nitrogen included in the barrier film
4
A is reacted with silicon included in the polysilicon film
3
, so that a reaction layer
6
of silicon nitride (SiN) with very high resistance can be formed between the polysilicon film
3
and the tungsten film
5
as shown in FIG.
8
C. As a result, the resistance of the gate electrode is disadvantageously increased.
As a countermeasure, Japanese Laid-Open Patent Publication No. 7-235542 describes that the sheet resistance of the reaction layer
6
can be lowered so as to lower the resistance of the gate electrode by setting the surface density of nitrogen included in the reaction layer
6
of silicon nitride to a predetermined value or less.
The present inventors, however, have found that the resistance of the gate electrode cannot be lowered even when the surface density of nitrogen included in the reaction layer
6
is set to the predetermined value or less in the electrode structure of the first conventional example.
Therefore, the present inventors have variously examined why the resistance of the gate electrode cannot be lowered in the electrode structure of the first conventional example, resulting in finding the following: When the thickness of the barrier film
4
A is reduced to approximately 0.1 through 1.0 nm for lowering the surface density of nitrogen included in the reaction layer
6
, the barrier film
4
A cannot exhibit the barrier function and tungsten silicide (WSi
x
) is formed, and hence, the resistance of the gate electrode cannot be lowered. On the other hand, when the thickness of the barrier film
4
A is larger than 1.0 nm, although the barrier function can be exhibited, the reaction layer
6
of silicon nitride with very high resistance is formed between the polysilicon film
3
and the tungsten film
5
. Therefore, the interface resistance between the polysilicon film
3
and the tungsten film
5
is increased.
Furthermore, since the tungsten nitride film has poor heat resistance, a large amount of nitrogen included in the tungsten nitride film is diffused through annealing carried out at 750° C. or more, so as to change the tungsten nitride film into a tungsten film.
In the case where the barrier film of titanium nitride is used as in the electrode structure of the second conventional example, a reaction layer
6
of silicon nitride with very high resistance is formed between the polysilicon film and the tungsten film. Therefore, the interface resistance between the polysilicon film
3
and the tungsten film
5
is increased.
As shown in
FIG. 9A
, a polysilicon film
3
is formed above a semiconductor substrate
1
with a gate insulating film
2
sandwiched therebetween, and the polysilicon film
3
is doped with a p-type dopant such as boron in forming a p-type gate electrode and with an n-type dopant such as phosphorus in forming an n-type gate electrode. In order to deposit a titanium nitride film
4
B on the polysilicon film
3
, the semiconductor substrate
1
is placed in a chamber in which a titanium target
7
including titanium as a principal constituent is disposed. Then, a mixed gas of an argon gas and a nitrogen gas is introduced into the chamber and discharge is caused in the chamber. In this manner, plasma is generated from the argon gas and the nitrogen gas, and nitrogen ions included in the plasma are reacted with silicon included in the polysilicon film
3
, so that a reaction layer
6
of silicon nitride can be formed in a surface portion of the polysilicon film
3
. The titanium target
7
is also nitrided so as to form a titanium nitride film
8
thereon, and titanium nitride is sputtered out from the titanium nitride film
8
so as to form a barrier film
4
B of titanium nitride on the reaction layer
6
as shown in FIG.
9
B.
Then, the semiconductor substrate
1
is placed in a chamber in which a tungsten target
9
including tungsten as a principal constituent is disposed, an argon gas is introduced into the chamber and discharge is caused in the chamber. In this manner, plasma is generated from the argon gas, and tungsten is sputtered out from the tungsten target
9
by argon ions included in the plasma, so that the sputtered tungsten can be deposited on the titanium nitride film
4
B. As a result, a tungsten film
5
is formed on the titanium nitride film
4
B as shown in FIG.
9
C.
Next, dopant layers serving as a source and a drain of the MOS transistor are formed in the semiconductor substrate
1
, and annealing is carried out at 750° C. or more for activating the dopant layers. Thus, excessive nitrogen included in the barrier film
4
B is diffused into an upper portion of the polysilicon film
3
as shown in FIG.
10
A. As a result, the thickness of the reaction layer
6
of titanium nitride is increased as shown in FIG.
10
B.
Also, the present inventors have examined the relationship between the annealing temperature and the interface resistance of the barrier film obtained after the annealing.
FIG. 11
shows the relationship between the annealing temperature (° C.) and the interface resistance (R
c
) between the polysilicon film and the metal film with a high melting point obtained after the annealing. In
FIG. 11
, the relationship obtained when a barrier film of tungsten nitride (WN
x
) is formed on an n-type polysilicon film (expressed as NPS) is plotted with &Circlesolid;, the relationship obtained when a barrier film of tungsten nitride is formed on a p-type polysilicon film (expressed as PPS) is plotted with &xcir
Matsumoto Michikazu
Sengoku Naohisa
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Soward Ida M.
Studebaker Donald R.
Zarabian Amir
LandOfFree
Method for fabricating electrode structure and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating electrode structure and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating electrode structure and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3006389