Method for fabricating dual-gate semiconductor device

Details Method for fabricating dual-gate semiconductor device Method for fabricating dual-gate semiconductor device

2005-12-20

2005-12-20

Wilson, Christian D. (Department: 2891)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S514000, C438S527000

Reexamination Certificate

active

06977207

ABSTRACT:
A method for fabricating a dual-gate semiconductor device is disclosed. The method A method for fabricating a dual-gate semiconductor device, the method comprising the steps: forming field oxide films defining an active region and a field region on a semiconductor substrate; forming a polysilicon layer on the semiconductor substrate having the field oxide films formed therein; forming a first photoresist pattern on the semiconductor substrate such that a portion of the polysilicon layer placed on the active region between the field oxide films is exposed; performing a first N+ion implantation process in the polysilicon layer using the first photoresist pattern as a mask; removing the first photoresist pattern; forming a second photoresist pattern on the polysilicon layer such that a portion of the polysilicon layer placed on the active region between the field oxide films is exposed; performing a second N+ion implantation process in the polysilicon layer using the second photoresist pattern as a mask; removing the second photoresist pattern; and subjecting the resulting substrate to a thermal diffusion process. The method allows poly depletion effect to be minimized, thereby ensuring stable threshold voltage and reducing actual failure rate.

REFERENCES:
patent: 6362055 (2002-03-01), Lin et al.
patent: 6387784 (2002-05-01), Chong et al.
patent: 6734070 (2004-05-01), Takahashi

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