Method for fabricating dual damascene

Details Method for fabricating dual damascene Method for fabricating dual damascene

1999-03-10

2000-12-05

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438654, H01L 2144

Patent

active

061566489

ABSTRACT:
A method for fabricating a dual damascene structure. A cap layer and a dielectric layer are formed in sequence over a substrate having a first conductive layer. A trench and a via hole are formed in the dielectric layer. The via hole is aligned under the trench. A barrier spacer is formed on sidewalls of the trench and the via hole. The cap layer exposed by the via hole is removed. A conformal adhesion layer is formed over the substrate. A second conductive layer is formed over the substrate and fills the trench and the via hole. A portion of the second conductive layer and the adhesion layer are removed to expose the dielectric layer.

REFERENCES:
patent: 5821168 (1998-10-01), Jain
patent: 5891513 (1999-04-01), Dubin
patent: 5968333 (1999-10-01), Nogami
patent: 6017817 (2000-01-01), Chung
patent: 6040243 (2000-03-01), Li

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