Method for fabricating direct wafer bond Si/SiO.sub.2 /Si substr

Details Method for fabricating direct wafer bond Si/SiO.sub.2 /Si substr Method for fabricating direct wafer bond Si/SiO.sub.2 /Si substr

1998-09-22

2000-12-05

Niebling, John F.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

438455, 438459, 438977, H01L 2176

Patent

active

061566217

ABSTRACT:
A method for fabricating direct wafer bond Si/SiO.sub.2 /Si substrates in which trenches are etched into a rear side of a device wafer. Subsequently, the rear side of the device wafer is ground. The device wafer is then placed by its front side onto the carrier wafer and the wafers are cross-linked to each other. The method has the advantage that a trench depth is no longer defined by an inaccurate etching process but rather by a thinning-back process that can be precisely controlled.

REFERENCES:
patent: 5081061 (1992-01-01), Rouse et al.
patent: 5459104 (1995-10-01), Sakai
patent: 5686364 (1997-11-01), Ohki et al.
patent: 5773352 (1998-06-01), Hamajima

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