Method for fabricating conductors in integrated circuits

Details Method for fabricating conductors in integrated circuits Method for fabricating conductors in integrated circuits

1985-02-13

1986-03-11

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29591, 156646, 156652, 156656, 204192E, 427 88, 357 65, B44C 122, C03C 1300, C03C 2506, C23F 102

Patent

active

045754020

ABSTRACT:
A technique of patterning a conductive layer for interconnections in integrated circuits is disclosed. The technique enables fine line conductors to be fabricated. In accordance with the invention, a pattern for the conductors is etched into the surface of a substrate through the use of a patterned photoresist layer. The conductive layer is then deposited over the photoresist layer and into the pattern etched into the substrate surface. In intervening steps, only the portions of the conductive layer outside the depression of the pattern in the surface are removed; the portions of the conductive layer within the depression remains intact to provide the pattern of fine line conductors desired.

REFERENCES:
patent: 4251319 (1981-02-01), Bonnie et al.
patent: 4307179 (1981-12-01), Chang et al.
patent: 4532002 (1985-07-01), White
patent: 4541892 (1985-09-01), Jeuch

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