Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-02-27
2003-07-29
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S585000, C438S595000, C438S624000, C438S652000, C438S197000, C438S618000
Reexamination Certificate
active
06599821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a method for fabricating a conductive line pattern for a semiconductor device having a low sheet resistance, which is requisite for implementation of a high speed and highly integrated semiconductor device.
2. Description of the Background Art
As a semiconductor device is highly integrated more and more, a conductive line, and especially, the width of a gate electrode becomes narrower. Accordingly, as the width of the conductive line is reduced, its resistance is increased, which causes RC delay in the conductive line of the gate electrode.
RC delay in the conductive line of the gate electrode is a big obstacle to a market in which a device operated at a high speed is desperately required. Therefore, manufacturers of semiconductor devices have conducted much research in order to meet the requirement of the market.
Recently, as low resistance gate electrode structures, there have been proposed a W/WNx/poly-Si (poly-Si refers to a polycrystalline silicon layer), a W/TiN/poly-Si or a W/poly-Si structure. Among them, a gate electrode in the W/WNx/poly-Si structure is notable with its advantage in that its sheet resistance is lower by 40% than the W/TiN/poly-Si structure.
Nonetheless, the gate electrode in the W/WNx/poly-Si structure has the following problems. The WNx formed, as a barrier film is a thermally unstable material. Thus, if a following thermal process at a temperature of more than 800° C. is performed, its characteristics as a barrier film are destroyed, leading to a silicide reaction of tungsten and polysilicon. Accordingly, the resistance is rapidly increased and characteristics of a gate insulation film are easily degraded.
In order to improve such shortcomings, an amorphous WN/poly-Si structure of a gate electrode was also proposed.
As an example of a method for fabricating a gate electrode of the conventional art, a method for fabricating the WNx/poly-Si gate electrode structure will now be described.
First, as shown in
FIG. 1A
, a silicon oxide film
101
having a thickness of 65 Å, that is, a gate insulation film, is formed on the upper surface of a semiconductor substrate
100
by a thermal oxidation. Next, a polysilicon layer
102
having a thickness of 1000 Å is formed on the upper surface of the silicon oxide film
101
by a low pressure chemical vapor deposition (LPCVD), to which an impurity ion is injected. And then, a WNx film
103
having a thickness of 1000 Å is deposited on the upper surface of the polysilicon layer
102
.
The obtained structure of
FIG. 1A
is subject to a rapid thermal treatment annealing at the temperature of 800~1000° C. As the annealing is performed, the WNx film
103
is changed to a W film
103
a,
and a barrier film
105
having a thickness of about 1 nm is formed on the interface of the W film
103
a
and the polysilicon layer
102
.
The barrier film
105
is a silicon nitride obtained as nitride of the WNx film is diffused to the polysilicon layer
102
, its under layer, and mixed with the silicon.
The reason why the WNx film
103
was changed to the W film
103
a
is as follows. At the temperature of more than 800° C., WNx becomes thermally unstable so that it is easily separated to W and N. Part of the separated N is diffused to the polysilicon layer, its under layer, and the remaining nitrogen is dispersed in the air. Accordingly, the WNx film is changed to the W film
Next, as shown in
FIG. 1C
, the W film
103
a,
the barrier film
105
, the polysilicon layer
102
and the silicon oxide film
101
are selectively etched by using a photoresist mask, so as to form a gate electrode pattern
106
.
And, as shown in
FIG. 1D
, the structure of
FIG. 1C
is thermally treated at an atmosphere of H
2
O/H
2
to selectively oxidize the polysilicon layer
102
and the silicon substrate
100
, thereby forming an oxide film
107
. At this time, the marginal portion of the gate insulation film
101
under the polysilicon layer
102
is thick. Consequently, the marginal portion of the gate electrode to which electric field is concentrated is prevented from destroying.
However, the method for fabricating the gate electrode of the conventional art has the following problems.
When performing the step of annealing the WNx/poly-Si layer at the temperature of more than 800° C. to change it to W/SiN/poly-Si layer, the step of patterning the multi-layer of W/SiN/poly-Si to form the gate electrode pattern, and the step of performing the oxidation process of more than 800° in order to oxidize the polysilicon layer of the gate electrode pattern, the high temperature thermal treatments are performed twice. Thus, due to the repeatedly performed high temperature thermal treatments, the multi-layer conductive line film receives a thermal stress, resulting in the degradation of the reliability of the semiconductor device using such conductive line.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method for fabricating a conductive line pattern suitable for a high speed and highly integrated device.
Another object of the present invention is to provide a method for fabricating a conductive line pattern having a low sheet resistance.
Still another object of the present invention is to provide a method for fabricating a conductive line pattern of a semiconductor device that is capable of reducing the number of thermal treatment processes thereby improving the reliability of a semiconductor device.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a method for fabricating a conductive line pattern for a semiconductor device including the steps of: forming a first insulation film on the upper surface of a semiconductor substrate; forming a polysilicon layer on the upper surface of the first insulation film; forming a WNx film on the upper surface of the polysilicon layer; forming a second insulation film on the upper surface of the WNx film; patterning the second insulation film, the WNx film and the polysilicon layer, to form a conductive line pattern; and selectively oxidizing the polysilicon layer.
According to the method for fabricating a conductive line pattern for a semiconductor device, the step of selectively oxidizing the polysilicon layer is performed in a manner that the semiconductor substrate is thermally treated at a temperature of 800~1000° C. by using a mixture of gases of H
2
O/H
2
or a carrier gas of argon or nitrogen.
According to the method for fabricating a conductive line pattern for a semiconductor device, a partial pressure ratio of the mixture of gases of H
2
O/H
2
is in the range of 1×10
−6
~10.
According to the method for fabricating a conductive line pattern for a semiconductor device, during the selective oxidation, the WNx film is changed to a W film.
According to the method for fabricating a conductive line pattern for a semiconductor device, in the step of forming the WNx film, the WNx film is formed by a reactive sputtering at an atmosphere of mixture of gases that the ratio of N
2
/(N
2
+Ar) is 0.4.
According to the method for fabricating a conductive line pattern for a semiconductor device, in the step of forming the WNx film, a content of N of the WNx film is in the range of 5~55%.
The method for fabricating a conductive line pattern for a semiconductor device further includes the steps of: forming a third insulation layer on the upper surface of the conductive line pattern and of the semiconductor substrate; and anisotropic-etching the third insulation layer, to form a side wall spacer at the side wall of the conductive line pattern.
REFERENCES:
patent: 5907188 (1999-05-01), Nakajima et al.
patent: 5923999 (1999-07-01), Balasubramanyam et al.
patent: 6037639 (2000-03-01), Ahmad
patent: 6162741 (2000-12-01), Akasaka et al.
patent: 6165883 (2000-12-01), Hiura
patent: 6236093 (2001-05-01), Hiura
patent: 6
Guerrero Maria
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
Zarabian Amir
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