Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-12-30
2004-05-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06740572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating complementary metal oxide semiconductor (CMOS) transistor of a semiconductor device; and, more particularly, to a method for fabricating a CMOS transistor of a semiconductor device capable of preventing a gate from deteriorating by removing the gate oxide layer at the gate edge region by processing anisotropic wet etching after gate formation of the CMOS and source/drain formation processes are finished.
2. Description of the Related Art
Generally, a complementary metal oxide semiconductor (CMOS) transistor is composed of a P-channel metal oxide semiconductor (PMOS) with superior power consumption and a N-channel metal oxide semiconductor (NMOS) capable of high speed operation, a low degree of integration and a complex manufacturing process. However, it does have excellent power consumption.
Recently, the size of semiconductor devices has decreased and a high degree of integration with new semiconductor technology. Therefore, the active area is decreased by the higher integration of the semiconductor device as well as the resulting increase in the threshold voltage.
FIG. 1
is a cross-sectional view showing a NMOS transistor with a lightly doped drain (LDD) structure formed in accordance with a prior art.
As shown in
FIG. 1
, after a device isolation layer
11
is formed on a semiconductor substrate
10
, a gate oxide layer
12
, a gate electrode
13
and an etching stop layer
14
are deposited onto the device isolation layer
11
and the semiconductor substrate
10
. Thereafter, a gate is formed thereon and a side wall spacer
15
is formed on a side wall of the gate.
In a following step, after the formation of the gate, a light oxidation process is performed to alleviate the plasma damage of the gate oxide layer
12
. After an NMOS LDD photomasking process and an implant process are performed, an interlayer insulating layer
16
is deposited thereon.
At this time, as shown in the drawing, the highest N+ source/drain concentration is approximately 10
17
, N-LDD concentration of approximately 10
18
and an N-channel concentration is approximately 10
17
.
In such a concentration distribution, a space charge area between the P-well and the source/drain forms inclining toward the channel.
Although such an LLD structure in accordance with a prior art can minimize a hot carrier effect, it requires twice the amount of photomasking and implant processes during manufacturing increasing costs as well as reducing the channel length by dopants diffused toward the gate following a thermal process.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the above mentioned problems of the conventional method for manufacturing a semiconductor device and to provide a method for fabricating a CMOS transistor of a semiconductor device capable of preventing a gate oxide layer from a hot carrier by generating a void by forming an interlayer insulating layer after the gate oxide layer at a gate edge region is removed through a wet etching process, after a source/drain is formed by an implant process by using a gate sidewall spacer by omitting an LDD photomasking and an implant processes.
In accordance with a first embodiment of the present invention, there is provided a method for fabricating a complementary metal oxide semiconductor (CMOS) of a semiconductor device, including the steps of: forming a device isolation layer in a semiconductor substrate; performing an implant process to the semiconductor substrate to form an N-well and P-well; forming a gate oxide layer, a gate electrode and an etching stop layer on the semiconductor substrate sequentially; patterning the gate electrode and the etching stop layer into a predetermined configuration; depositing a gate oxide layer and an insulating layer having a high etching ratio on the patterned etching stop layer and a portion of the semiconductor substrate which is not covered by the patterned etching stop layer; etching the insulating layer to form a side wall spacer and to form a source/drain through an implant process; removing the gate oxide layer positioned around a gate edge through a wet etching process by using the side wall spacer and the etching stop layer as an etching barrier layer; and depositing an interlayer insulating layer on the patterned etching stop layer, the side wall spacer and a portion of the semiconductor substrate which is not covered with the patterned etching stop layer and the side wall spacer.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein after the oxidation layer of the gate edge portion is etched, and a light oxidation process is performed.
In accordance with a second embodiment of the present invention, there is provided a method for fabricating a complementary metal oxide semiconductor (CMOS) of a semiconductor device, including the steps of: forming a device isolation layer in a semiconductor substrate; performing an implant process to the semiconductor substrate to form an N-well and P-well; forming a gate oxide layer and a gate electrode on the semiconductor substrate sequentially; patterning the gate electrode and the gate oxide layer into a predetermined configuration; removing the gate oxide layer placed at an edge portion of a gate by the wet etching; forming an insulting layer on the patterned gate electrode and a portion of the semiconductor substrate; forming a side wall spacer on a side wall of the patterned gate electrode by etching the insulating layer; and forming a source/drain in the semiconductor substrate through an implant process.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein the insulating layer has a high etching ratio.
REFERENCES:
patent: 6127251 (2000-10-01), Gardener et al.
“Silicon Processing for the VLSI ERA”, vol. 3: The Submicron Mosfet, Stanley Wolf Ph.D., Lattice Press, Sunset Beach, CA, 1984, pp. 591-598.
Hoang Quoc
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
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