Method for fabricating closed vias in a printed circuit board

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C257SE23067

Reexamination Certificate

active

07427562

ABSTRACT:
A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer. Resin from one dielectric layer fills the cavities of approximately one half of the closed vias, and resin from the other dielectric layer fills the circular cavities of the remainder of the closed vias. The total amount of resin migrated from each of the dielectric layers into the closed via cavities is approximately equal.

REFERENCES:
patent: 5263243 (1993-11-01), Taneda et al.
patent: 6039889 (2000-03-01), Zhang
patent: 6282782 (2001-09-01), Biunno et al.
patent: 6841080 (2005-01-01), Kingon et al.
patent: 6921505 (2005-07-01), Lee et al.
patent: 2003/0121700 (2003-07-01), Schmidt
patent: 2003/0178388 (2003-09-01), Phillips
patent: 2004/0108137 (2004-06-01), Vetter et al.
patent: 2006/0121722 (2006-06-01), Card
patent: 2006/0193105 (2006-08-01), Sakata et al.
patent: 2007/0139294 (2007-06-01), Dunn et al.
patent: 2007/0148829 (2007-06-01), Yoshino et al.

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