Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2010-05-27
2011-11-15
Smoot, Stephen W (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S464000, C257SE21503
Reexamination Certificate
active
08058100
ABSTRACT:
A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.
REFERENCES:
patent: 5892179 (1999-04-01), Rinne et al.
patent: 6103552 (2000-08-01), Lin
patent: 6271469 (2001-08-01), Ma et al.
patent: 6287893 (2001-09-01), Elenius et al.
patent: 6350668 (2002-02-01), Chakravorty
patent: 6433427 (2002-08-01), Wu et al.
patent: 7002245 (2006-02-01), Huang et al.
patent: 2004/0241039 (2004-12-01), Hwang
patent: 2006/0006760 (2006-01-01), Namba et al.
patent: 2008/0265440 (2008-10-01), Mahler
patent: 2006/005304 (2006-01-01), None
Hsiao Cheng-Hsu
Huang Chien-Ping
Pu Han-Ping
Corless Peter F.
Edwards Wildman Palmer LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
Smoot Stephen W
LandOfFree
Method for fabricating chip scale package structure with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating chip scale package structure with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating chip scale package structure with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4294984