Method for fabricating cell plugs of semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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C438S656000, C438S675000

Reexamination Certificate

active

06667228

ABSTRACT:

RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. P2001-32904 filed Jun. 12, 2001, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating cell plugs of a semiconductor device, which reduces cell plug resistance and thereby increases the reading/writing operation speed of the semiconductor device.
2. Discussion of the Related Art
A method for fabricating cell plugs of a semiconductor device according to a related art will be described with reference to the accompanying drawings. Particularly,
FIGS. 1A
to
1
G are sectional views illustrating process steps for fabricating cell plugs of a Metal-Insulator-Metal (MIM) Structure according to a related art.
As shown in
FIG. 1A
, a plurality of gates
12
are formed on a predetermined region of a semiconductor substrate
11
. An insulating film is deposited on the entire surface of the semiconductor substrate
11
including the gates
12
. The insulating film is then selectively removed to form insulating film sidewalls
13
on both sides of the gates
12
.
Then, although not shown, impurity ions are injected into a predetermined region of the semiconductor substrate
11
so as to form source/drain impurity regions in the semiconductor substrate
11
at both sides of the gates
12
adjacent the insulating film sidewalls
13
.
Afterwards, a first insulating interlayer
14
of a predetermined thickness is deposited on the entire surface of the semiconductor substrate
11
. The first insulating interlayer
14
is then polished by an etch-back or chemical mechanical polishing (CMP) process to expose upper portions of the gates
12
.
Then, the first insulating interlayer
14
is selectively removed so that a portion above the semiconductor substrate
11
corresponding the source/drain impurity region between the gates
12
is exposed to define a first contact hole
17
a
through the first insulating interlayer
14
. A polysilicon or monosilicon film is buried in the first contact hole
17
a
to form a first cell plug
15
.
Subsequently, a second insulating interlayer
16
is deposited on the entire surface of the semiconductor substrate
11
and selectively removed by photolithography or etching processes. This exposes an upper surface of the first cell plug
15
and its adjacent regions to define a second contact hole
17
b
through the second insulating interlayer
16
.
Then, as shown in
FIG. 1B
, a second cell plug material
18
is deposited on the entire surface of the semiconductor substrate
11
including the second contact hole
17
b
. In this case, a monosilicon or polysilicon film is used as the second cell plug material
18
.
Then, as shown in
FIG. 1C
, the second cell plug material
18
on an upper portion of the second insulating interlayer
16
is selectively removed to remain only in the second contact hole
17
b
. This forms a second cell plug
18
a
. In this case, the second cell plug material
18
is removed by an etch-back or CMP process.
Then, as known, a silicide contact as well as a barrier metal are formed between a storage node and the second cell plug
18
a
to produce a MIM structure. In this process, to define regions for forming the silicide contact and the barrier metal, as shown in
FIG. 1D
, the upper portion of the second cell plug
18
a
is removed by a thickness of several tens of nm by an etch-back process. Then, as shown in
FIG. 1E
, a silicide contact
19
made of a titanium silicide film is formed on the exposed upper surface of the second cell plug
18
a
. This can be accomplished by depositing a titanium film using a physical vapor deposition (PVD) process, annealing the titanium film to cause silicon in the second cell plug
18
a
to react with the titanium in the titanium film, and removing portions of the titanium film that do not react with silicon. In the alternative, the silicide contact
19
can be formed by using an in-situ titanium silicide deposition process through a chemical vapor deposition (CVD) process.
Then, as shown in
FIG. 1F
, a titanium nitride film
20
is deposited on the entire surface of the semiconductor substrate
11
including the silicide contact
19
. Subsequently, as shown in
FIG. 1G
, the titanium nitride film
20
on the upper portion of the second insulating interlayer
16
is selectively removed by an etch-back or CMP process so as to form a barrier film
20
a
on the silicide contact
19
. Then, a MIM capacitor (not shown) is formed, which comes into contact with the barrier film
20
a
. This completes the method of fabricating the cell plugs of a semiconductor device having a MIM structure according to the related art.
These are, however, at least several problems that are associated with such conventional methods. First, silicon of high specific resistance is used as cell plug materials for the first and second cell plugs
15
and
18
a
. This increases the cell plug resistance of the semiconductor device (e.g., memory device) in accordance with the design rules of the semiconductor device. An increase in the cell plug resistance is a problem because it decreases the reading/writing operation speed of the semiconductor device.
Second, in order to form the silicide contact
19
and the barrier film
20
a
between a lower electrode of the MIM capacitor and the second cell plug
18
a
, the conventional method requies complicated processes such as an etch-back process for forming the second cell plug
18
a
, processing steps including a polishing process for forming the barrier film
20
a
, etc. As a result, the conventional method of fabricating cell plugs involves complex and multiple steps and requires lengthy processing time.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device with cell plugs and a method for fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating cell plugs of a semiconductor device, which can increase an operation speed of a semiconductor memory device and simplify the fabrication process.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating cell plugs of a semiconductor device according to one embodiment of the present invention, includes the steps of forming a first insulating interlayer on a semiconductor substrate whereby a predetermined lower pattern is formed, forming a first cell plug connected to the semiconductor substrate by passing through the first insulating interlayer, forming a second insulating interlayer on the entire surface of the semiconductor substrate, forming a contact hole on the second insulating interlayer so that an upper surface of the first cell plug is exposed, forming a silicide contact on the exposed surface of the first cell plug, forming a second cell plug material on the entire surface including the contact hole, and removing the second cell plug material on the second insulating interlayer through a polishing process so as to form a second cell plug in the contact hole.
In accordance with one embodiment, the present invention is directed to a method for fabricating a semiconductor device having cell plugs, the method comprising the steps of forming a first insulating interlayer on a semiconductor substrate,

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