Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-12-13
2001-01-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S239000, C438S396000
Reexamination Certificate
active
06171941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more particularly, to a method for fabricating a capacitor having a dielectric layer of a ferroelectric constant or a high dielectric constant, which is suitable for a high-density, high-speed memory device.
2. Discussion of the Related Art
The adoption of various ferroelectric substances for the fabrication of the capacitor dielectric in a semiconductor memory device has enabled development of large-scale memory devices without the refresh requirements of conventional DRAM devices. Among ferroelectric substances, SrBi
2
Ta
2
O
9
(SBT) has recently been the subject of active research, due to its superior fatigue strength, a favorable degree of magnetic susceptibility, and low leakage current properties.
In most cases, platinum is used for the electrodes forming the capacitor. Before and after the evaporation and etching steps for electrode formation, an annealing process is carried out to achieve crystallization and recovery, which improves the dielectric characteristics and magnetization properties of the SBT layer. The annealing process is performed several times repeatedly in a high temperature oxygen atmosphere of 800° C.
Due to the lack of a diffusion-inhibiting layer, which is a thin protective layer capable of withstanding the high temperature oxygen atmosphere of the annealing process, a non-polysilicon plug structure is frequently adopted for interconnection between the substrate and the capacitor's lower electrode.
Such a capacitor structure, however, is not without its problems. For example, to reduce the generation of a platinum residue and polymers during the etching process for forming the upper electrode of the capacitor, titanium nitride is used for the upper electrode as a hard mask, which, undesirably, oxidizes and forms a film of titanium dioxide during the annealing process for recovery of the SBT layer's characteristics after etching. Then, since the titanium dioxide forms a rough and porous surface and exhibits insulation properties, the upper electrode must be completely rid of the titanium dioxide when a contact hole is formed for metal interconnection. In addition, the poor surface conditions of titanium dioxide causes subsequent layer formations, e.g., wiring, to experience lifting when annealing and cleaning processes are performed.
Moreover, in forming the metal interconnection, titanium is deposited atop the platinum upper electrode to attain an ohmic contact between the metal interconnection and the active region of the substrate. The deposited titanium is diffused to the SBT layer and resides along a grain boundary of the platinum (upper electrode) layer, degrading the remnant polarization value of the SBT layer and reducing its fatigue strength. To resolve the diffusion problem, the metal interconnection (wiring) process needs to be performed separately, which requires additional mask fabrication and evaporation and etching steps, making the process very complicated.
Therefore, an improved method for fabricating the capacitor of a semiconductor memory device is needed.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for fabricating a capacitor of a semiconductor memory device, using titanium aluminum nitride as a diffusion inhibiting layer of the upper electrode.
It is another object of the present invention to provide a method for fabricating a capacitor of a semiconductor memory device, in which a diffusion of titanium to the grain boundary of the upper electrode of the capacitor is effectively inhibited.
It is yet another object of the present invention to provide a method for fabricating a capacitor of a semiconductor memory device, in which a diffusion inhibiting layer of the upper electrode is highly resistant to high temperature and oxidation.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a method for fabricating a capacitor of a semiconductor memory device, the capacitor having a platinum upper layer for forming an upper electrode, the method comprising forming a titanium aluminum nitride layer, satisfying Ti
1-x
Al
x
N where x<1, on the platinum upper layer.
Capacitor fabrication is realized by the steps of: forming a first insulation layer on a substrate; forming a first conductive layer on the insulation layer; forming a dielectric layer on the first conductive film; forming a second conductive layer on the dielectric layer; forming the titanium aluminum nitride layer on the second conductive layer; selectively etching the titanium aluminum nitride layer, the second conductive layer, the dielectric layer, and the first conductive layer, to form a capacitor pattern; performing an annealing process to the etched capacitor pattern in an oxygen atmosphere; forming a second insulation layer over the annealed capacitor pattern; forming a first contact hole by selectively etching the second insulation layer, to expose an aluminum oxide layer formed on the surface of the titanium aluminum nitride layer, and forming a second contact hole by selectively etching the second insulation layer and the first insulation layer, to expose an active region of the substrate; removing the exposed portion of the aluminum oxide layer; and forming a metal interconnection to connect the second conductive layer of the capacitor and to connect the substrate, through the first and second contact holes, respectively.
REFERENCES:
patent: 5231306 (1993-07-01), Meikle et al.
patent: 5504041 (1996-04-01), Summerfelt
patent: 5525542 (1996-06-01), Maniar et al.
patent: 5618746 (1997-04-01), Hwang
patent: 5729054 (1998-03-01), Summerfelt et al.
patent: 5858851 (1999-01-01), Yamagata et al.
patent: 5930639 (1999-07-01), Schuele et al.
patent: 6025205 (2000-02-01), Park et al.
Lee Sang-hyeob
Park Dae-gyu
Dang Phuc T.
Hyundai Electronic Industries Co. Ltd.
Nelms David
Oliff & Berridg,e PLC
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