Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-11
2003-03-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S514000, C438S629000, C438S637000, C438S641000, C438S651000, C438S239000, C438S386000, C257S068000, C257S618000
Reexamination Certificate
active
06531395
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89120452, filed Oct. 2, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a method for fabricating bitlines and, in particular, a method for fabricating bitlines having reduced contact resistance.
2. Description of Related Art
A typical fabrication process for DRAM devices is the so-called 4P2M process that incorporates four layers of polysilicon and two layers of metal interconnections. The first of the four polysilicon layers employed, as viewed from the bottom of the substrate, is the polysilicon layer for the transistor gate electrode. The second layer is the polysilicon for the bitline. The third layer is the bottom electrode of the storage capacitor of the memory cell unit, while the fourth is the polysilicon for the top electrode of the storage capacitor. On the other hand, the two layers of metal interconnections are used to connect all the circuitry configurations embedded in the substrate, including the four polysilicon layers.
For the fabrication of the bitlines in typical DRAM devices, polycide made from the composition of doped polysilicon and tungsten silicide (WSi
x
) is frequently used to form the electrical conducting wiring in the device. As a material for the contact plugs for DRAM bitlines, tungsten silicide is advantageous in that the phenomenon of static charge capacitance can be reduced in order to improve the device operating speed.
However, if the contact surface between the second polysilicon layer and the first polysilicon layer in the contact opening is not well-formed and rugged, contact resistance between the bitline and the wordline increases. Moreover, if the same situation (ragged contact surface) happens to the contact surface between the bitline and the diffusion region, contact resistance between the bitline and the diffusion region increases.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for fabricating bitlines, which reduces contact resistance between the bitline and the wordline as well as contact resistance between the bitline and the diffusion region.
The invention achieves the above-identified object by providing a method for fabricating bitlines, including the following steps: providing a semiconductor substrate having a contact opening which exposes a diffusion region in the substrate or a polysilicon layer of a wordline; forming a polysilicon layer to cover the opening and contact the exposed surface of the diffusion region or the exposed polysilicon layer of the wordline; forming a tungsten silicide layer to cover the polysilicon layer; performing a ion implantation step with high energy and high dosage to damage a contact surface between the bitline and the wordline or a contact surface between the bitline and the diffusion region; forming a better contact surface between the bitline and the wordline or a better contact surface between the bitline and the diffusion region using thermal annealing in the subsequent steps, thereby reducing contact resistance between the bitline and the wordline or between the bitline and the diffusion region.
Following the method provided in the invention, bitlines with reduced contact resistance are formed, avoiding the prior art problem of increased contact resistance due to uncompleted contact surface of the bitline. Furthermore, there is no extra annealing step, just using the annealing step in the subsequent processes, so that the thermal budget does not increase at all. The method provided in the invention is therefore compatible with the present manufacture processes used.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4978634 (1990-12-01), Shen et al.
patent: 5099297 (1992-03-01), Hazani
patent: 5364814 (1994-11-01), McQueen
patent: 5384478 (1995-01-01), Hong
patent: 5461536 (1995-10-01), Beach et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5981330 (1999-11-01), Jenq
patent: 6221762 (2001-04-01), Byun et al.
patent: 6235630 (2001-05-01), Akram et al.
patent: 6242308 (2001-06-01), Hsieh et al.
patent: 6281064 (2001-08-01), Mandelman et al.
patent: 6303437 (2001-10-01), Liu
patent: 6316344 (2001-11-01), Jenq
patent: 6399447 (2002-06-01), Clevenger et al.
patent: 1-087-443 (2000-09-01), None
Nam et al. “A novel simplified process for fabricating a very high density p-channel trench gate power mosfet” IEEE Electron devices letters vol. 21 No. 7 Jul. 2000, p. 363-367.*
Nam et al. “A novel simplified process for fabricating a very high density p-channel trench gate power mosfet” IEEE electron device letters vol. 21 No. 7 Jul. 2000, pp. 365-367.
Hou Alex
Wu King-Lung
Lee Jr. Granvill D
Smith Matthew
United Microelectronics Corp.
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