Method for fabricating bipolar transistor in integrated circuit

Details Method for fabricating bipolar transistor in integrated circuit Method for fabricating bipolar transistor in integrated circuit

1986-08-26

1987-11-10

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156648, 156657, 1566611, 156662, 357 34, 357 43, 437 33, 437193, 437200, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

047055995

ABSTRACT:
In a method for fabricating a bipolar transistor in accordance with the present invention, a base electrode (9a) of metal silicide is formed being separated from an emitter region (7) only by the thickness of a double-layered insulator film (109, 203).

REFERENCES:
patent: 4445268 (1984-05-01), Hirao
patent: 4484388 (1984-11-01), Iwasaki
patent: 4486942 (1984-12-01), Hirao
S. P. Murarka, Silicides for VLSI Applications, pp. 66-69, 1983, Academic Press.
"Subnanosecond Self-Aligned l.sup.2 L/MTL Circuits", D. D. Tang et al, IEEE Transactions on Electron Device, vol. ED-27, No. 8, Aug. 1980, pp. 1379-1384.

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