Fishing – trapping – and vermin destroying
Patent
1986-10-30
1987-10-20
Hearn, Brian E.
Fishing, trapping, and vermin destroying
148DIG126, 437 40, H01L 2174, H01L 2178, H01L 2180
Patent
active
047004606
ABSTRACT:
A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped. The silicon that is between the insulated gate and each wafer surface includes a relatively lightly doped voltage-supporting region contiguous with the insulated gate and the laterally adjacent silicon and a relatively heavily doped region between this voltage-supporting region and the surface. Additionally, the interface between the insulated gate and the laterally adjacent silicon has a low density of interface states.
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Dolny Gary M.
Goodman Lawrence A.
Glick K. R.
Hearn Brian E.
Morris B. E.
RCA Corporation
Thomas Tom
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