Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-03-07
2006-03-07
Everhart, Caridad (Department: 2891)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S950000
Reexamination Certificate
active
07008856
ABSTRACT:
A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant region, forms spacers on sidewalls of the pad nitride layer pattern, removes some part of the pad oxide layer and the top portion of the substrate through an etching process using the spacers as a mask to form a trench that divides the ion implant region into two parts. The example fabrication method also forms a gap filling insulating layer over the resulting substrate, and forms a trench isolation layer and junction regions simultaneously by removing the spacers, the pad nitride layer pattern, the pad oxide layer, and the top portion of the gap filling insulating layer.
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patent: 6277697 (2001-08-01), Lee
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patent: 10-2001-0088298 (2001-12-01), None
Han Chang Hun
Kim Bong Kil
DongbuAnam Semiconductor
Everhart Caridad
Hanley Flight & Zimmerman LLC
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