Method for fabricating and identifying integrated circuits...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S128000, C438S129000, C438S598000

Reexamination Certificate

active

06649505

ABSTRACT:

BACKGROUND
This invention relates to methods for fabricating integrated circuits, and to the resulting circuits.
Three-dimensional integrated circuits include multiple stacked layers of electrical or optical devices, all supported by a single underlying substrate. Such a three-dimensional arrangement substantially increases the device density of the integrated circuit.
Many such three-dimensional integrated circuits are fabricated with a greater or lesser number of stacked layers, depending upon the number of devices required in the final integrated circuit. For example, a 64 MB memory array may be made of 8 stacked layers of memory cells, while a 32 MB memory array may be made up of 4 stacked layers of memory cells.
A need presently exists for methods for enhancing the flexibility with which such three-dimensional integrated circuits can be fabricated and for reducing the cost of such integrated circuits.
SUMMARY
By way of general introduction, the preferred embodiments described below allow two or more topologically different integrated circuits to be formed using the same set of photolithographic masks for the lower device layers. First integrated circuits include a larger number of vertically stacked layers of devices and employ the full set of masks, and second integrated circuits have a smaller number of vertically stacked layers of devices and use a subset of the full set of masks. Because the same masks are used to fabricate the lower device layers of both the first and second integrated circuits, fabrication is made substantially more flexible and costs are reduced.
The preferred embodiments described below include at least one voltage source on a top layer of the integrated circuit, at least one sensing contact on one of the lower layers of the integrated circuit, and at least one conductive path. Each conductive path extends between the respective voltage source and sensing contact for integrated circuits having a respective set of device layers, but the conductive path does not provide continuity between the respective voltage source and sensing contact for other integrated circuits lacking some or all of the respective set of layers. A switch such as a multiplexer is controlled as a function of the voltage on each sensing contact such that the switch selects a circuit identification signal from a first set when the sensed signal on the sensing contact is in a first range of values, and a circuit identification signal from a second set when the sensed signal on the sensing contact is in a second range of values. In this way, the switch supplies the appropriate circuit identification signal as an output signal, without requiring different masks for the fabrication of the first and second integrated circuits. Multiple sensing contacts can be used to switch among three or more circuit identification signals, as described below.
The foregoing paragraphs have been provided by way of general introduction, and they are not intended to narrow the scope of the following claims.


REFERENCES:
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patent: 2003/0086284 (2003-05-01), Johnson
patent: WO 99/14763 (1999-03-01), None
“Exotic memories, diverse approaches,” EDN ASIA, Sep. 2001, pp. 22-33.
MAPLD 99, “Laser-formed Vertical Metallic Link and Potential Implementation in Digital Logic Integration,” Zhang et al., 19 pages (1999).

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