Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-05-10
2003-04-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S396000, C438S791000, C438S954000, C438S381000, C438S761000, C438S762000
Reexamination Certificate
active
06548425
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating an ONO layer of a nitride read only memory (NROM) cell.
2. Description of the Prior Art
A read only memory (ROM) device, comprising a plurality of memory cells, is a type of semiconductor wafer device that functions in data storage. The ROM device is widely applied in computer data storage and memory devices, and depending on the method of storing data, the ROM can be divided into several types such as a mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and an electrically erasable programmable ROM (EEPROM).
Differing from other types of ROMs that use a polysilicon or metal floating gate, a nitride read only memory (NROM) uses an insulating dielectric layer as a charge-trapping medium. Due to the highly compacted nature of the silicon nitride layer, hot electrons tunneling from the MOS transistor into the silicon nitride layer are trapped within to form an unequal concentration distribution to increase data reading speed and to avoid current leakage.
Please refer to
FIG. 1
of a schematic diagram of a standard structure of an NROM according to the prior art. A semiconductor wafer
10
comprises a P-type silicon substrate
12
, two N-type doped areas
14
,
16
positioned on the surface of the silicon substrate
12
, an ONO dielectric structure
24
, and a gate conductor layer
26
positioned on the ONO dielectric structure
24
. The ONO dielectric structure
24
is comprises a bottom oxide layer
18
, a silicon nitride layer
20
and a top oxide layer
22
.
Please refer to FIG.
2
and FIG.
3
. FIG.
2
and
FIG. 3
are schematic diagrams of a method for fabricating an NROM using the standard structure shown in FIG.
1
. As shown in
FIG. 2
, according to the prior art for fabricating a gate of the NROM, a semiconductor wafer
30
comprising a P-type silicon
32
is first provided. A high temperature oxidation process is then performed to form an oxide layer with a thickness of 50-150 angstroms as a bottom oxide layer
34
on the surface of the silicon substrate
32
. Then, a low-pressure chemical vapor deposition (LPCVD) is used to deposit a silicon nitride layer
36
with a thickness of 50-150 angstroms on the bottom oxide layer
34
. An annealing process is used under a high temperature of 950° C. for a duration of 30 minutes to repair the structure of the silicon nitride layer
36
. Also, water steam is injected to perform a wet oxidation process to form a silicon oxy-nitride layer with a thickness of 50-150 angstroms as a top oxide layer
38
. The bottom oxide layer
34
, the silicon nitride layer
36
and the top oxide layer
38
compose the ONO dielectric structure
40
on the surface of the silicon substrate
32
.
As shown in
FIG. 3
, a photolithographic and etching process is performed to form a gate pattern in the top oxide layer
38
and silicon nitride layer
36
. An ion implantation process is then performed to form a plurality of doped areas
42
as a source and drain in the MOS transistor. Thereafter, a thermal oxidation process is used to form a field oxide (FOX)
44
on the surface of the source/drain to isolate each silicon nitride layer
36
. Finally, a doped polysilicon layer
46
is deposited as a gate conductor layer.
In the structure of the NROM according to the prior art, a silicon nitride layer is used as a charge trapping medium. However, the charge trapping efficiency of the silicon nitride layer is not good, so the trapped charges distribute widely in the silicon nitride layer. Moreover, trapped charges may leak from the silicon nitride layer resulting in a leakage current under the influence of vertical fields. Due to the wider charge distribution, incomplete erasing or a long erasing time is easily incurred in the subsequent erase state operation. Therefore, the life span and reliability of the NROM will be greatly affected.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of fabricating an ONO layer comprising a plurality of nitride layers, so as to improve the life span and reliability of the NROM.
In accordance with the claim invention, the method comprises firstly forming a first oxide layer on the surface of the substrate of a semiconductor wafer. Then two chemical vapor deposition (CVD) processes are performed to form a first nitride layer and a second nitride layer, respectively on the surface of the first oxide layer, with the boundary between the second nitride layer and the first nitride layer forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer. The second oxide layer, the second nitride layer, the first nitride layer and the first oxide layer together construct the ONO layer.
The present invention uses the interface between the two silicon nitride layers as a deep charge trapping center so as to improve the charge trapping efficiency of the floating gate of the NROM, and furthermore, to improve the endurance and reliability of the NROM.
REFERENCES:
patent: 4814291 (1989-03-01), Kim et al.
patent: 4882649 (1989-11-01), Chen et al.
patent: 5460991 (1995-10-01), Hong
patent: 5498890 (1996-03-01), Kim et al.
patent: 6204142 (2001-03-01), Thakur
patent: 6274902 (2001-08-01), Kauffman et al.
Chang Kent Kuohua
Tseng Uway
Hsu Winston
Macronix International Co. Ltd.
Smith Matthew
Yevsikov V.
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