Method for fabricating an NPN transistor in a BICMOS technology

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...

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438317, 438341, 438348, 438350, H01L 21331

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active

061566160

ABSTRACT:
The present invention relates to a bipolar transistor of NPN type implemented in an epitaxial layer within a window defined in a thick oxide layer, including an opening formed substantially at the center of the window, this opening penetrating into the epitaxial layer down to a depth of at least the order of magnitude of the thick oxide layer, an N-type doped region at the bottom of the opening, a first P-type doped region at the bottom of the opening, a second lightly-doped P-type region on the sides of the opening, and a third highly-doped P-type region in the vicinity of the upper part of the opening, the three P-type regions being contiguous and forming the base of the transistor.

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French Search Report from French Patent Application 96 14411, filed Nov. 19, 1996.
French Search Report from French Patent Application 96 14412, filed Nov. 19, 1996.

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