Method for fabricating an interconnect

Details Method for fabricating an interconnect Method for fabricating an interconnect

1999-12-20

2001-08-21

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S723000, C438S724000, C438S740000, C438S743000, C438S744000, C438S756000, C438S757000

Reexamination Certificate

active

06277755

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for an interconnect structure of an integrated circuit. More particularly, the present invention relates to a fabrication method for an inter-metal dielectric layer.
2. Description of the Related Art
The multilevel interconnect structure has been widely employed to accommodate the continuing demand in the integrated circuit manufacturing to produce a more powerful and highly integrated device in a smaller area. In such an interconnect structure, a conductive material, for example, a metal line, on one interconnect level is electrically insulated from a patterned conductive material on the other interconnect level by an inter-metal dielectric (IMD) layer. Connections between the conductive material on the various levels of the interconnect are made by forming an opening, which is often referred as a via, in the inter-metal dielectric layer to expose a certain portion of the underlying metal line. A conductive contact, also known as a via plug, is then formed in the via to connect the underlying metal line with the overlying metal line. The via and the via plug thus serve to enable an electrical contact between the conductive materials at various interconnect levels.
According to the conventional fabrication method for an interconnect structure by means of a dual damascene manufacturing process, a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer are sequentially formed on a substrate to serve as the inter-metal dielectric layer. Photolithography and etching are further conducted to form a trench line in the second silicon oxide layer. During the definition of the trench line, the silicon nitride layer serves as an etch stop layer, preventing an over-etch from occurring during the formation of the trench line. Photolithography and etching are further conducted to define the silicon nitride layer and the first silicon oxide layer, thereby to form a via under the trench line. A copper layer is then subsequently formed to fill the trench line and the via. These processing steps are then repeated to form the next level of the interconnect.
A consequence of having multiple layers of the patterned conductive material separated by an insulating layer is the formation of an undesired parasitic capacitance. The presence of parasitic capacitance in microelectronic devices contributes to adverse effects such as RC delay, power dissipation and cross-talk. The silicon nitride layer, which is a part of the inter-metal dielectric layer and also plays a role as an etch stop during the formation of the trench line, has a dielectric constant (k) of about 7, which significantly increases the inter-metal dielectric (IMD) capacitance.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides a fabrication method for an interconnect structure, wherein the IMD capacitance of the inter-metal dielectric layer is lower. The issues relating to a high IMD capacitance, such as RC delay, power dissipation and cross-talk, are thus mitigated. The inter-metal dielectric layer, which comprises a gradient silicon oxy-nitride layer, can also serve as an etch-stop during the oxide etching process.
The present invention provides a dual damascene process for an interconnect structure, wherein the inter-metal dielectric layer has a lower dielectric constant and can serve as an etch-stop during the oxide-etching process when forming the trench line. The method includes forming a first silicon oxide layer on a substrate. A gradient silicon oxy-nitride layer is then formed on the first silicon oxide layer, wherein the silicon oxy-nitride layer possesses an oxide-like property at the bottom and a silicon nitride-like property gradually increases towards the top of the silicon oxy-nitride layer. A second silicon oxide layer is further formed on the gradient silicon oxy-nitride layer. Photolithography and etching are then conducted on the second silicon oxide layer while using the silicon oxy-nitride layer as an etch-stop to form a trench line in the second silicon oxide layer. Photolithography and etching are again conducted on the silicon oxy-nitride layer, followed by removing the first silicon oxide layer and forming a via under the trench line. A conductive material is then formed, filling the trench line and the via simultaneously.
According to this embodiment of the present invention, a gradient silicon oxy-nitride layer is formed, wherein the silicon oxy-nitride layer possesses an oxide-like property at the bottom, and a silicon nitride property gradually increases towards the top of the silicon oxy-nitride layer. As a result, the silicon oxy-nitride layer can serve as an etch-stop layer during the oxide etching process when forming the trench line. Since the dielectric constant at the bottom of the gradient oxy-nitride layer is about 7 to about 4.2, the overall IMD capacitance is thereby reduced. The problems relating to a high IMD capacitance, such as RC time delay, power dissipation and cross-talk, are thus mitigated.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5821153 (1998-10-01), Tsai et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5989957 (1999-11-01), Ngo et al.
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6040619 (2000-03-01), Wang et al.

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