Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2002-03-14
2003-09-02
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S381000, C438S396000, C438S397000, C438S398000, C438S399000, C438S253000, C438S254000, C438S255000, C438S256000
Reexamination Certificate
active
06613640
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to an integrated ferroelectric semiconductor memory having a ferroelectric capacitor module formed according to the stack cell principle on an intermediate oxide layer above a selection transistor located in or on a semiconductor wafer. The capacitor module is conductively connected by its bottom electrode to an electrode of the selection transistor by means of an electrically conductive plug formed in a contact hole leading through the intermediate oxide. A conductive oxygen diffusion barrier is provided directly below the bottom capacitor electrode in order to protect the plug from oxygen diffusion and a conductive adhesion layer is provided below the oxygen diffusion barrier, of which the adhesion layer and the overlying oxygen diffusion barrier fill the contact hole at least in its upper region and form the plug there.
The invention further pertains to a method for fabricating an integrated ferroelectric semiconductor memory according to the stack cell principle, in which a ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer which capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. The method, generically, comprises the following steps: a layer system comprising a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the conductive plug at least in the region lying directly below the bottom capacitor electrode.
Such a ferroelectric semiconductor memory and such a fabrication method are disclosed in German patent DE 198 42 684 C1 (cf. copending, commonly assigned patent application Ser. No. 09/941,910).
In ferroelectric semiconductor memories fabricated according to the stack cell principle, the transistors are typically fabricated on the wafer and then an intermediate oxide layer is deposited over them. The ferroelectric capacitors are fabricated on this intermediate oxide above the selection transistors. The connection between transistors and capacitors is achieved by means of a plug which fills a contact hole which penetrates through the intermediate oxide layer, which plug is situated directly below the capacitor in the case of the stack cell principle.
In order to condition the ferroelectric layer, it is necessary to carry out a heat treatment in an oxygen atmosphere at temperatures of up to 800° C. (ferro-anneal). During this heat treatment, the plug, which usually comprises polysilicon or tungsten, must be protected from oxidation, since such oxidation can irreversibly interrupt the electrical connection between the capacitor module and the selection transistor. Moreover, reactions between the capacitor electrodes, the ferroelectric and the plug are to be avoided if they impair the functionality of the chip.
All products with ferroelectric layers that are commercially available at the present time are constructed according to the offset cell principle and have an integration density of only a few kilobits through to one megabit. In this case, the contact between the plug and the electrode is avoided during the ferro-anneal. However, the result is a significantly larger standard cell.
In order to prevent the oxidation of the plug in ferroelectric semiconductor memories constructed according to the stack cell principle, layer systems have been introduced which act inter alia as an oxygen diffusion barrier. However, even with the use of an oxygen diffusion barrier (also cf. FIG.
1
), it is very difficult to produce a permanently conductive contact between a bottom electrode and the selection transistor, because an adhesion layer lying below the diffusion barrier can be oxidized from the side during the oxygen heat treatment of the ferroelectric.
In the above-mentioned German patent DE 198 42 684 C1 the electrically conductive plug which connects the bottom capacitor electrode to an electrode of a selection transistor is formed from an electrically conductive material deposited into the contact hole, e.g. from doped polysilicon, tungsten, tantalum, titanium, titanium nitride or tungsten silicide, and an overlying oxygen diffusion barrier.
U.S. Pat. No. 6,146,941 (German published patent application DE 198 38 741 A1) describes a capacitor and a process wherein in a contact window that is open toward a source/drain region of a selection window, firstly an adhesion/barrier layer made of Ti/TiNx, which covers the bottom and the sidewall of the contact window and the top side of an insulating layer, and a metallic bottom capacitor electrode above the adhesion/barrier layer are deposited directly into the contact window.
German published patent application DE 199 26 501 A1 (cf. copending, commonly assigned patent application Ser. No. 10/013,234) discloses a method for fabricating a ferroelectric or DRAM semiconductor memory device in which Ir/IrOx is used as oxygen diffusion barrier in combination with adhesion layers.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a fabrication method for an integrated ferroelectric semiconductor memory according to the stack cell principle and such an integrated ferroelectric semiconductor memory according to the stack cell principle, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which is improved such that the oxidation of the polysilicon or tungsten material of the plug and of the adhesion layer during the oxygen heat treatment of the ferroelectric can be reliably prevented.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated ferroelectric semiconductor memory, comprising:
an intermediate oxide layer above a selection transistor located in or on a semiconductor wafer and a ferroelectric capacitor module formed according to a stack cell principle on the intermediate oxide layer and having a bottom electrode;
an electrically conductive plug formed in a contact hole leading through the intermediate oxide layer and connecting the bottom electrode of the capacitor module to an electrode of the selection transistor;
a conductive oxygen diffusion barrier of Ir and IrOx directly below the bottom electrode for protecting the plug from oxygen diffusion and a conductive adhesion layer below the oxygen diffusion barrier, the adhesion layer and the oxygen diffusion barrier filling the contact hole at least in an upper region thereof and forming the plug in the upper region;
the oxygen diffusion barrier including an Ir layer in the contact hole and an IrOx layer covering the contact hole above the Ir layer.
In accordance with an added feature of the invention, the plug consists of, i.e., is formed exclusively of, the adhesion layer and the oxygen diffusion barrier.
In accordance with an additional feature of the invention, the plug comprises a first segment disposed directly above the selection transistor electrode and formed of a material selected from the group consisting of polysilicon and tungsten, and a second segment above the first segment formed of the adhesion layer and the oxygen diffusion layer.
In accordance with another feature of the invention, the contact hole has a beveled sidewall tapering downward toward the selection transistor.
In accordance with a further feature of the invention, the adhesion layer comprises Ti.
With the above and other objects in view there is also provided, in accordance with the invention, a method of fabricating an integrated ferroelectric semiconductor memory according to the stack cell principle, wherein a ferroelectric capacitor module is formed on an intermediate
Kasko Ihar
Krönke Matthias
Weinrich Volker
Berry Renee R.
Greenberg Laurence A.
Ho Hoai
Infineon - Technologies AG
Mayback Gregory L.
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