Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-02-03
1999-09-07
Brown, Peter Toby
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438618, 438622, 257522, 257758, H01L 2144
Patent
active
059501022
ABSTRACT:
A method for making air-insulated planar metal interconnections having low interlevel capacitance with improved RC time delays for integrated circuits is achieved. The method involves using a multilayer of negative and positive photoresists in which open regions are developed in the negative photoresist for the metal interconnections, and open regions are developed in the positive photoresist for via holes. The open regions are then filled with a Ti/TiN diffusion barrier deposited at room temperature and an electroless plated copper, and polished back using a Dual Damazene to form the interconnecting metal level and the via hole stud. The method is repeated several times to form multilevel metal interconnections. The remaining photoresist is then totally removed by oxygen ashing to leave a free-standing multilevel metal interconnection structure that is conformally coated with a thin Al.sub.2 O.sub.3 passivation layer and having air insulation. This results in a much lower inter- and intralevel capacitance and improved circuit performance.
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Ackerman Stephen B.
Brown Peter Toby
Industrial Technology Research Institute
Oh Edwin
Saile George O.
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