Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
2002-09-20
2004-04-06
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C257S059000, C257S072000, C257S347000
Reexamination Certificate
active
06716660
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a wiring line assembly and a method for fabricating the same and, more particularly, to a wiring line assembly used for a thin film transistor array substrate for a liquid crystal display.
(b) Description of the Related Art
Generally, wiring lines for a semiconductor device or a display device are used for signal transmission, and hence, it becomes important lines to keep such wiring away from signal delays as much as possible.
Particularly, as a large-size high-resolution liquid crystal display develops, it becomes more important that the thin film transistor array substrate for such a liquid crystal display should involve low resistance wiring lines to minimize the signal delay. For instance, a low resistance metal such as Al or Al alloy may be used for the wiring purpose.
However, the Al or Al alloy-based wiring lines bear a weak physical or chemical characteristic. The Al or Al alloy erodes easily at the contacting area, when contacting other conductive materials.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a thin film transistor array substrate that has a wiring line assembly bearing low resistance and good adhesion characteristics.
This and other objects may be achieved by a thin film transistor array substrate having a wiring line assembly with the following features.
The wiring line assembly is formed with an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements. Each of the alloy elements bears a low melting point.
Each of the alloy elements each bear a diffusion coefficient of 1.5E-12 cm
2
/sec or more. The alloy elements each bear a melting point of 1500K or less. The wiring line assembly is formed with an Ag alloy comprising Ag and at least one of alloy elements and the alloy elements each bearing a low melting point. The composition content ratio of the alloy elements to the Ag alloy is 20at % or less. The alloy elements are selected from the group consisting of Li, Mg, Al, Sm, and Mn. The Ag alloy is used for reflection electrodes for a reflection type liquid crystal display.
According to one aspect of the present invention, the thin film transistor array substrate basically includes a gate line assembly based on an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bear a low melting point. The gate line assembly comprises a gate electrode and a gate line. A data line assembly crosses over the gate line assembly while being insulated from the gate line assembly. The data line assembly comprises a source electrode, a drain electrode and a data line. A semiconductor layer contacts the source electrode and the drain electrode. The semiconductor layer forms a thin film transistor together with the gate electrode, the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode.
Herein the data line assembly may be based on an Ag alloy. The Ag alloy for the data line assembly comprises Ag and at least one of alloy elements and the alloy elements each bear a low melting point. The alloy elements bear a diffusion coefficient of 1.5E-12 cm
2
/sec or more. The alloy elements each bear a melting point of 1500K or less. The composition content ratio of the alloy elements to the Ag alloy is 20at % or less. The alloy elements may be selected from the group consisting of Li, Mg, Al, Sm, and Mn.
Herein, the thin film transistor array substrate further comprises an insulating substrate under the gate line assembly, a gate insulating layer covering the gate line assembly and being under the semiconductor layer, and a protective layer covering the data line assembly with a contact hole exposing the drain electrode. The drain electrode is placed on the semiconductor layer together with the source electrode and the pixel electrode is connected to the drain electrode through the contact hole. The semiconductor layer is formed of hydrogenated amorphous silicon.
Herein, the thin film transistor array substrate further comprises an alloy element—oxide layer. The alloy element—oxide layer being interposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.
And, the thin film transistor array substrate further comprises an insulating substrate under the semiconductor layer having a source region, a drain region and a channel region, a gate insulating layer covering the semiconductor layer and being under the gate line assembly, an inter-layered insulating layer covering the gate line assembly in which the inter-layered insulating layer and the gate insulating layer have contact holes exposing the source region and the drain region and the source and the drain electrodes are connected to the source and the drain regions through the contact holes, and a protective layer covering the data line assembly with a contact hole exposing the drain electrode in which the pixel electrode is connected to the drain electrode through the contact hole of the protective layer. The semiconductor layer is formed with poly-crystalline silicon.
The thin film transistor array substrate further comprises an alloy element-oxide layer. The alloy element—oxide layer is interposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.
In a method for fabricating the thin film transistor array substrate, a gate line assembly is formed on an insulating substrate with an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bearing a low melting point. The gate line assembly comprises a gate electrode and a gate line. A gate insulating layer is formed on the substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer is formed on the gate insulating layer. A data line assembly is formed on the semiconductor layer. The data line assembly comprises a source electrode, a drain electrode and a data line. A protective layer is formed on the substrate such that the protective layer covers the data line assembly. A contact hole exposing the drain electrode is formed in the protective layer. A pixel electrode is formed on the protective layer such that the pixel electrode is connected to the drain electrode through the contact hole.
Herein, The data line assembly is formed with an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements each bearing a low melting point. The gate line assembly is formed through depositing an Ag alloy layer onto the substrate through sputtering a target of the Ag alloy with an oxygen concentration of 5000 ppm or less. The Ag alloy layer is patterned through a photolithography. The protective layer is formed through heat treatment at 200° C. or more. The alloy element of the Ag alloy layer for the data line assembly reacts with a silicon oxide layer to form an alloy element—oxide layer during the process of heat treatment for forming the protective layer where the silicon oxide layer is naturally formed on the semiconductor layer.
Also, in a method for fabricating the thin film transistor array substrate, a semiconductor layer is formed on an insulating substrate. A gate insulating layer is formed on the substrate such that the gate insulating layer covers the semiconductor layer. A gate line assembly is formed on the gate insulating layer with an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bear a low melting point. The gate line assembly comprises a gate electrode and a gate line. A source and a drain region are formed through doping the semiconductor layer with impurities and while defining a channel region. An inter-layered insulating layer is formed on the substrate such that the inter-layered insulating layer covers the gate line assembly. Contact holes exposing the source and the drain regions are formed in the inter-layered insulating layer and the gate insulating layer. A data line assembly i
Cho Beom-Seok
Jeong Chang-Oh
Lee Jae-Gab
Fahmy Wael
Ha Nathan W.
McGuireWoods LLP
Samsung Electronics Co,. Ltd.
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