Method for fabricating a warpage-preventive circuit board

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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Details

C029S825000, C029S829000, C029S831000, C029S849000, C174S255000, C174S536000, C257S691000, C257S701000, C257S735000, C257S773000

Reexamination Certificate

active

11043496

ABSTRACT:
A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

REFERENCES:
patent: 5134246 (1992-07-01), Beppu et al.
patent: 6204559 (2001-03-01), Lin et al.
patent: 6323438 (2001-11-01), Ito
patent: 6380633 (2002-04-01), Tsai
patent: 6476331 (2002-11-01), Kim et al.
patent: 6507100 (2003-01-01), Valluri et al.
patent: 6534852 (2003-03-01), Lin et al.
patent: 8-51258 (1996-02-01), None
patent: 2001-326429 (2001-11-01), None

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