Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2003-03-17
2004-06-15
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S210000, C438S243000, C438S253000, C438S396000, C438S389000, C438S392000
Reexamination Certificate
active
06750111
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method of fabricating a trench capacitor. The invention relates in particular to a trench capacitor having improved leakage current properties and an associated fabrication method with simplified process steps for forming an insulation collar.
FIG. 1
is a simplified sectional view of a DRAM semiconductor memory cell with a trench capacitor in accordance with the prior art, as is disclosed for example in the Published European Patent Application No. EP 0 949 680 A2. In accordance with
FIG. 1
, a conventional DRAM (Dynamic Random Access Memory) semiconductor memory cell has a trench capacitor
160
formed in a substrate
101
. The trench capacitor
160
essentially includes a trench
108
filled with a conductive filling material
161
as a second capacitor plate. In the vicinity of a lower region of the trench
108
, a buried plate
165
is formed as a first capacitor plate in the substrate
101
. The buried plate may be formed for example by diffusion from an ASG (arsenosilicate glass) layer. Situated between the buried plate
165
serving as first capacitor plate and the filling material
161
serving as second capacitor plate there is a dielectric layer
164
for lining the lower region of the trench
108
and for forming a capacitor dielectric.
Furthermore, the DRAM semiconductor memory cell has a field-effect transistor
110
, which has a gate
112
and also source and drain diffusion regions
113
and
114
. The diffusion regions
113
and
114
are isolated from one another by a channel
117
, the diffusion region
114
being connected to the trench capacitor
160
via a contact region
125
.
In order to avoid undesirable leakage currents, an insulation collar or simply collar
168
is situated on an upper region of the trench capacitor
160
or of the trench
108
.
A buried well or layer
170
is situated below the surface of the substrate
101
and essentially serves as a connection between the buried plates
165
of the respective adjacent DRAM semiconductor memory cells in the memory cell array.
In order to control the respective DRAM semiconductor memory cells or the memory array, each cell has a bit line and also a word line. Usually, the gates
112
form a word line, while the diffusion region
113
is connected to a bit line
185
via a contact
183
. In this case, the bit line
185
is isolated from the diffusion region by an insulating layer
189
.
In accordance with
FIG. 1
, respectively adjacent DRAM semiconductor memory cells are isolated from one another by a shallow trench isolation (STI). A word line
120
lies not only above the actual transistor
110
but also above the trench
108
. A “folded bit line architecture” is thereby obtained. However, the invention described below is not restricted to an architecture of this type.
FIGS. 2A
to
2
C show essential method steps for forming the insulation collar
168
in accordance with the prior art. Identical reference symbols designate identical or similar elements or layers which are only described once in detail.
In accordance with
FIG. 2A
, firstly the trench
108
is formed in the semiconductor substrate
101
with the aid of a “pad stack”
107
. The pad stack
107
includes, for example, a pad oxide layer
104
and a pad stop layer
105
, on which a hard mask layer (not illustrated) can be superposed. An oxide layer (SiO
2
) or boundary layer
151
serving as an etching stop layer or barrier layer preferably has a thickness of 5 to 50 nm and can be formed by deposition or ca be formed thermally. A detailed description of the method for forming the pad stack
107
or the trench
108
is dispensed with at this point since it essentially corresponds to a conventional method.
Furthermore, in accordance with
FIG. 2A
, a sacrificial filling material
152
, composed of polysilicon for example, is formed in a lower region of the trench
108
. A coplanar insulation collar layer
167
is subsequently formed on the surface of the wafer and in the trench
108
. This conformal insulation collar layer
167
or collar layer is formed for example through the use of a chemical deposition method (CVD, chemical vapor deposition), an oxide having a constant thickness of approximately 2 to 10 nm preferably being deposited. A densification is subsequently carried out in order to improve the properties of the insulation collar layer
167
, the densification taking place for example at a temperature of approximately 1000° C. in an N
2
or Ar environment.
In accordance with
FIG. 2B
, in a subsequent method step the insulation collar layer
167
or the collar is patterned, a reactive ion etching (RIE) preferably being carried out, using CF
4
, CHF
3
or C
4
F
8
for example. In accordance with
FIG. 2B
, after this patterning step no insulation collar layer
167
remains on the pad stack
107
, as a result of which the insulation collar
168
is essentially formed. During this method step, the sacrificial filling material
152
is simultaneously uncovered in the trench
108
, in order thus to allow to remove the sacrificial filling material
152
.
In accordance with
FIG. 2C
, in a subsequent method step, the sacrificial filling material
152
and the boundary layer
151
are completely removed in the lower region of the trench
108
(in particular if a thermal oxide (SiO
2
) and/or a deposited oxide is used as the boundary layer
151
, then it can be preserved as a barrier layer in the upper region of the trench
108
), which may also result in the insulation collar
168
being etched back in its upper region. In the worst-case situation during such a method step, the insulation collar
168
is etched back on its top side to such an extent that the semiconductor substrate
101
is uncovered and the substrate
101
is etched in an upper region of the trench
108
. The probability of the substrate
101
being undesirably uncovered in such a way is also increased if, by way of example, the trench is extended in the lower region of the trench
108
. The functioning of the DRAM semiconductor memory cell is thereby significantly impaired or completely prevented. Furthermore, with the use of vapor phase doping for forming the buried plate
165
, at the uncovered silicon edge, a highly doped region can likewise be formed in an undesirable manner, such that the functioning of the semiconductor memory cell once again suffers as a result.
Since, in the method described above, the insulation collar layer
167
is completely removed from the pad stack
107
, a part of the pad stack
107
is eroded in the course of a subsequent overetching process for ensuring a sufficient opening to the sacrificial filling material
152
. Such erosion of the pad nitride or the pad stack
107
in the cell array and in planar support regions (not illustrated) takes place non-uniformly, which is why planarization in particular of the shallow trench isolation (STI) in subsequent process steps is made more difficult. Furthermore, a predetermined minimum thickness of the pad stack or of the pad nitride layer as etching stop layer is necessary for the shallow trench isolation or the STI oxide
180
, so that an initial thickness of the pad stack or pad nitride increased by the erosion thickness is usually required. This increased pad stack thickness in turn requires a longer mask opening process for the trench
108
(deep trench mask open process), which consumes more resist, as a result of which a thicker resist layer becomes necessary. However, a thicker resist layer in turn adversely affects the process window of trench lithography, which can lead to a reduced yield.
Furthermore, the pad stack
107
can likewise be eroded during subsequent etching processes, which can once again lead to losses of yield. Moreover, in the event of facetting of the stop layer or pad nitride layer
105
(greatly tapered pad nitride layer
105
at the edge of the trench), the substrate may be uncovered above the upper insulation collar edge. Such a pad nitride facetting usually arises during a trench
Fourson George
Garcia Joannie Adelle
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
LandOfFree
Method for fabricating a trench capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a trench capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a trench capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3326154