Method for fabricating a transistor with a gate structure

Details Method for fabricating a transistor with a gate structure Method for fabricating a transistor with a gate structure

2005-08-09

2005-08-09

Loke, Steven (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S595000, C438S588000, C438S778000

Reexamination Certificate

active

06927154

ABSTRACT:
A gate structure of a transistor is fabricated with an additional barrier formed on a metal layer of the gate structure before the deposition of a silicon oxide layer. Applying this barrier layer on the metal layer before the deposition of the silicon oxide layer prevents an oxidation of the metal during the deposition of the silicon oxide layer. A lowering of the conductivity of the metal layer or a loss of metal through sublimating metal oxide is thereby prevented. As a result, in particular the performance of the gate structure or of the transistor is improved further. In addition, disturbing coupling effects in the circuit are significantly reduced by the use of the silicon oxide cap.

REFERENCES:
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patent: 5998290 (1999-12-01), Wu et al.
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patent: 6455441 (2002-09-01), Beaman
patent: 6465335 (2002-10-01), Kunikiyo
“W/WNX/Poly-Si Gate Technology for Future High Speed Deep Submicron CMOS LSIs” by Kasai et al., IEDM 94, pp. 497-500.
“Semiconductor Devices-Physics and Technology” by Sze, 1985, pp. 360-362.
“Semiconductor Devices-Physics and Technology” by Sze, pp. 357-360.

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